1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 /***************************************************************************
4 * Generic Xtensa target *
5 * Copyright (C) 2019 Espressif Systems Ltd. *
6 ***************************************************************************/
8 #ifndef OPENOCD_TARGET_XTENSA_H
9 #define OPENOCD_TARGET_XTENSA_H
12 #include <target/target.h>
13 #include <target/breakpoints.h>
14 #include "xtensa_regs.h"
15 #include "xtensa_debug_module.h"
19 * Holds the interface to Xtensa cores.
22 #define XT_ISNS_SZ_MAX 3
24 #define XT_PS_RING(_v_) ((uint32_t)((_v_) & 0x3) << 6)
25 #define XT_PS_RING_MSK (0x3 << 6)
26 #define XT_PS_RING_GET(_v_) (((_v_) >> 6) & 0x3)
27 #define XT_PS_CALLINC_MSK (0x3 << 16)
28 #define XT_PS_OWB_MSK (0xF << 8)
30 #define XT_LOCAL_MEM_REGIONS_NUM_MAX 8
32 #define XT_AREGS_NUM_MAX 64
33 #define XT_USER_REGS_NUM_MAX 256
35 #define XT_MEM_ACCESS_NONE 0x0
36 #define XT_MEM_ACCESS_READ 0x1
37 #define XT_MEM_ACCESS_WRITE 0x2
39 enum xtensa_mem_err_detect
{
40 XT_MEM_ERR_DETECT_NONE
,
41 XT_MEM_ERR_DETECT_PARITY
,
42 XT_MEM_ERR_DETECT_ECC
,
45 struct xtensa_cache_config
{
50 enum xtensa_mem_err_detect mem_err_check
;
53 struct xtensa_local_mem_region_config
{
56 enum xtensa_mem_err_detect mem_err_check
;
60 struct xtensa_local_mem_config
{
62 struct xtensa_local_mem_region_config regions
[XT_LOCAL_MEM_REGIONS_NUM_MAX
];
65 struct xtensa_mmu_config
{
67 uint8_t itlb_entries_count
;
68 uint8_t dtlb_entries_count
;
73 struct xtensa_exception_config
{
78 struct xtensa_irq_config
{
83 struct xtensa_high_prio_irq_config
{
89 struct xtensa_debug_config
{
97 struct xtensa_tracing_config
{
100 bool reversed_mem_access
;
103 struct xtensa_timer_irq_config
{
108 struct xtensa_config
{
115 uint8_t miscregs_num
;
124 uint16_t user_regs_num
;
125 const struct xtensa_user_reg_desc
*user_regs
;
126 int (*fetch_user_regs
)(struct target
*target
);
127 int (*queue_write_dirty_user_regs
)(struct target
*target
);
128 struct xtensa_cache_config icache
;
129 struct xtensa_cache_config dcache
;
130 struct xtensa_local_mem_config irom
;
131 struct xtensa_local_mem_config iram
;
132 struct xtensa_local_mem_config drom
;
133 struct xtensa_local_mem_config dram
;
134 struct xtensa_local_mem_config uram
;
135 struct xtensa_local_mem_config xlmi
;
136 struct xtensa_mmu_config mmu
;
137 struct xtensa_exception_config exc
;
138 struct xtensa_irq_config irq
;
139 struct xtensa_high_prio_irq_config high_irq
;
140 struct xtensa_timer_irq_config tim_irq
;
141 struct xtensa_debug_config debug
;
142 struct xtensa_tracing_config trace
;
143 unsigned int gdb_general_regs_num
;
144 const unsigned int *gdb_regs_mapping
;
147 typedef uint32_t xtensa_insn_t
;
149 enum xtensa_stepping_isr_mode
{
150 XT_STEPPING_ISR_OFF
, /* interrupts are disabled during stepping */
151 XT_STEPPING_ISR_ON
, /* interrupts are enabled during stepping */
154 /* Only supported in cores with in-CPU MMU. None of Espressif chips as of now. */
160 XT_MODE_ANY
/* special value to run algorithm in current core mode */
163 struct xtensa_sw_breakpoint
{
164 struct breakpoint
*oocd_bp
;
166 uint8_t insn
[XT_ISNS_SZ_MAX
];
167 /* original insn size */
168 uint8_t insn_sz
; /* 2 or 3 bytes */
171 #define XTENSA_COMMON_MAGIC 0x54E4E555U
174 * Represents a generic Xtensa core.
177 unsigned int common_magic
;
178 const struct xtensa_config
*core_config
;
179 struct xtensa_debug_module dbg_mod
;
180 struct reg_cache
*core_cache
;
181 unsigned int regs_num
;
182 /* An array of pointers to buffers to backup registers' values while algo is run on target.
183 * Size is 'regs_num'. */
184 void **algo_context_backup
;
185 struct target
*target
;
187 enum xtensa_stepping_isr_mode stepping_isr_mode
;
188 struct breakpoint
**hw_brps
;
189 struct watchpoint
**hw_wps
;
190 struct xtensa_sw_breakpoint
*sw_brps
;
192 bool permissive_mode
; /* bypass memory checks */
193 bool suppress_dsr_errors
;
195 /* Sometimes debug module's 'powered' bit is cleared after reset, but get set after some
196 * time.This is the number of polling periods after which core is considered to be powered
197 * off (marked as unexamined) if the bit retains to be cleared (e.g. if core is disabled by
198 * SW running on target).*/
199 uint8_t come_online_probes_num
;
200 bool regs_fetched
; /* true after first register fetch completed successfully */
203 static inline struct xtensa
*target_to_xtensa(struct target
*target
)
206 struct xtensa
*xtensa
= target
->arch_info
;
207 assert(xtensa
->common_magic
== XTENSA_COMMON_MAGIC
);
211 int xtensa_init_arch_info(struct target
*target
,
212 struct xtensa
*xtensa
,
213 const struct xtensa_config
*cfg
,
214 const struct xtensa_debug_module_config
*dm_cfg
);
215 int xtensa_target_init(struct command_context
*cmd_ctx
, struct target
*target
);
216 void xtensa_target_deinit(struct target
*target
);
218 static inline bool xtensa_addr_in_mem(const struct xtensa_local_mem_config
*mem
, uint32_t addr
)
220 for (unsigned int i
= 0; i
< mem
->count
; i
++) {
221 if (addr
>= mem
->regions
[i
].base
&&
222 addr
< mem
->regions
[i
].base
+ mem
->regions
[i
].size
)
228 static inline bool xtensa_data_addr_valid(struct target
*target
, uint32_t addr
)
230 struct xtensa
*xtensa
= target_to_xtensa(target
);
232 if (xtensa_addr_in_mem(&xtensa
->core_config
->drom
, addr
))
234 if (xtensa_addr_in_mem(&xtensa
->core_config
->dram
, addr
))
236 if (xtensa_addr_in_mem(&xtensa
->core_config
->uram
, addr
))
241 int xtensa_core_status_check(struct target
*target
);
243 int xtensa_examine(struct target
*target
);
244 int xtensa_wakeup(struct target
*target
);
245 int xtensa_smpbreak_set(struct target
*target
, uint32_t set
);
246 int xtensa_smpbreak_get(struct target
*target
, uint32_t *val
);
247 int xtensa_smpbreak_write(struct xtensa
*xtensa
, uint32_t set
);
248 int xtensa_smpbreak_read(struct xtensa
*xtensa
, uint32_t *val
);
249 xtensa_reg_val_t
xtensa_reg_get(struct target
*target
, enum xtensa_reg_id reg_id
);
250 void xtensa_reg_set(struct target
*target
, enum xtensa_reg_id reg_id
, xtensa_reg_val_t value
);
251 int xtensa_fetch_all_regs(struct target
*target
);
252 int xtensa_get_gdb_reg_list(struct target
*target
,
253 struct reg
**reg_list
[],
255 enum target_register_class reg_class
);
256 int xtensa_poll(struct target
*target
);
257 void xtensa_on_poll(struct target
*target
);
258 int xtensa_halt(struct target
*target
);
259 int xtensa_resume(struct target
*target
,
261 target_addr_t address
,
262 int handle_breakpoints
,
263 int debug_execution
);
264 int xtensa_prepare_resume(struct target
*target
,
266 target_addr_t address
,
267 int handle_breakpoints
,
268 int debug_execution
);
269 int xtensa_do_resume(struct target
*target
);
270 int xtensa_step(struct target
*target
, int current
, target_addr_t address
, int handle_breakpoints
);
271 int xtensa_do_step(struct target
*target
, int current
, target_addr_t address
, int handle_breakpoints
);
272 int xtensa_mmu_is_enabled(struct target
*target
, int *enabled
);
273 int xtensa_read_memory(struct target
*target
, target_addr_t address
, uint32_t size
, uint32_t count
, uint8_t *buffer
);
274 int xtensa_read_buffer(struct target
*target
, target_addr_t address
, uint32_t count
, uint8_t *buffer
);
275 int xtensa_write_memory(struct target
*target
,
276 target_addr_t address
,
279 const uint8_t *buffer
);
280 int xtensa_write_buffer(struct target
*target
, target_addr_t address
, uint32_t count
, const uint8_t *buffer
);
281 int xtensa_checksum_memory(struct target
*target
, target_addr_t address
, uint32_t count
, uint32_t *checksum
);
282 int xtensa_assert_reset(struct target
*target
);
283 int xtensa_deassert_reset(struct target
*target
);
284 int xtensa_breakpoint_add(struct target
*target
, struct breakpoint
*breakpoint
);
285 int xtensa_breakpoint_remove(struct target
*target
, struct breakpoint
*breakpoint
);
286 int xtensa_watchpoint_add(struct target
*target
, struct watchpoint
*watchpoint
);
287 int xtensa_watchpoint_remove(struct target
*target
, struct watchpoint
*watchpoint
);
288 void xtensa_set_permissive_mode(struct target
*target
, bool state
);
289 int xtensa_fetch_user_regs_u32(struct target
*target
);
290 int xtensa_queue_write_dirty_user_regs_u32(struct target
*target
);
291 const char *xtensa_get_gdb_arch(struct target
*target
);
294 COMMAND_HELPER(xtensa_cmd_permissive_mode_do
, struct xtensa
*xtensa
);
295 COMMAND_HELPER(xtensa_cmd_mask_interrupts_do
, struct xtensa
*xtensa
);
296 COMMAND_HELPER(xtensa_cmd_smpbreak_do
, struct target
*target
);
297 COMMAND_HELPER(xtensa_cmd_perfmon_dump_do
, struct xtensa
*xtensa
);
298 COMMAND_HELPER(xtensa_cmd_perfmon_enable_do
, struct xtensa
*xtensa
);
299 COMMAND_HELPER(xtensa_cmd_tracestart_do
, struct xtensa
*xtensa
);
300 COMMAND_HELPER(xtensa_cmd_tracestop_do
, struct xtensa
*xtensa
);
301 COMMAND_HELPER(xtensa_cmd_tracedump_do
, struct xtensa
*xtensa
, const char *fname
);
303 extern const struct reg_arch_type xtensa_user_reg_u32_type
;
304 extern const struct reg_arch_type xtensa_user_reg_u128_type
;
305 extern const struct command_registration xtensa_command_handlers
[];
307 #endif /* OPENOCD_TARGET_XTENSA_H */
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