1 ################################################################################
2 # Atmel AT91SAM9260-EK eval board
4 # http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3933
6 # Atmel AT91SAM9260 : PLLA = 198.656 MHz, MCK = 99.328 MHz
7 # OSCSEL configured for external 32.768 kHz crystal
9 # 32-bit SDRAM : 2 x Micron MT48LC16M16A2, 4M x 16Bit x 4 Banks
11 ################################################################################
13 # We add to the minimal configuration.
14 source [find target/at91sam9260.cfg]
16 # By default S1 is open and this means that NTRST is not connected.
17 # The reset_config in target/at91sam9260.cfg is overridden here.
18 # (or S1 must be populated with a 0 Ohm resistor)
19 reset_config srst_only
21 $_TARGETNAME configure -event reset-start {
22 # At reset CPU runs at 32.768 kHz.
23 # JTAG Frequency must be 6 times slower if RCLK is not supported.
26 # RSTC_MR : enable user reset, MMU may be enabled... use physical address
27 mww phys 0xfffffd08 0xa5000501
30 $_TARGETNAME configure -event reset-init {
31 mww 0xfffffd44 0x00008000 # WDT_MR : disable watchdog
33 mww 0xfffffc20 0x00004001 # CKGR_MOR : enable the main oscillator
35 mww 0xfffffc30 0x00000001 # PMC_MCKR : switch to main oscillator
37 mww 0xfffffc28 0x2060bf09 # CKGR_PLLAR: Set PLLA Register for 198.656 MHz
39 mww 0xfffffc30 0x00000101 # PMC_MCKR : Select prescaler (divide by 2)
41 mww 0xfffffc30 0x00000102 # PMC_MCKR : Clock from PLLA is selected (99.328 MHz)
44 # Increase JTAG Speed to 6 MHz if RCLK is not supported
47 arm7_9 dcc_downloads enable # Enable faster DCC downloads
49 mww 0xfffff870 0xffff0000 # PIO_ASR : Select peripheral function for D15..D31
50 mww 0xfffff804 0xffff0000 # PIO_PDR : Disable PIO function for D15..D31
52 mww 0xffffef1c 0x00010002 # EBI_CSA : Assign EBI Chip Select 1 to SDRAM, VDDIOMSEL set for +3V3 memory
54 mww 0xffffea08 0x85227259 # SDRAMC_CR : Configure SDRAM (2 x Micron MT48LC16M16A2 : 4M x 16Bit x 4 Banks)
56 mww 0xffffea00 0x1 # SDRAMC_MR : issue a NOP command
58 mww 0xffffea00 0x2 # SDRAMC_MR : issue an 'All Banks Precharge' command
60 mww 0xffffea00 0x4 # SDRAMC_MR : issue 8 x 'Auto-Refresh' Command
76 mww 0xffffea00 0x3 # SDRAMC_MR : issue a 'Load Mode Register' command
78 mww 0xffffea00 0x0 # SDRAMC_MR : normal mode
80 mww 0xffffea04 0x2b6 # SDRAMC_TR : Set refresh timer count to 7us
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