2 # http://cogcomp.com/csb_csb337.htm
4 source [find target/at91rm9200.cfg]
6 # boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
7 flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
9 # ETM9 trace port connector present on this board, 16 data pins.
10 if { [info exists ETM_DRIVER] } {
11 etm config $_TARGETNAME 16 normal half $ETM_DRIVER
12 # OpenOCD may someday support a real trace port driver...
13 # system config file would need to configure it.
15 etm config $_TARGETNAME 16 normal half dummy
16 etm_dummy config $_TARGETNAME
19 proc csb337_clk_init { } {
20 # CPU is in Slow Clock Mode (32KiHz) ... needs slow JTAG clock
23 # CKGR_MOR: start main oscillator (3.6864 MHz)
27 # CKGR_PLLAR: start PLL A for CPU and peripherals (184.32 MHz)
28 mww 0xfffffc28 0x20313e01
29 # CKGR_PLLBR: start PLL B for USB timing (96 MHz, with div2)
30 mww 0xfffffc2c 0x12703e18
34 # PMC_MCKR: switch to CPU clock = PLLA, master clock = CPU/4
38 # CPU is in Normal Mode ... allows faster JTAG clock speed
42 proc csb337_nor_init { } {
43 # SMC_CSR0: adjust timings (10 wait states)
44 mww 0xffffff70 0x1100318a
49 proc csb337_sdram_init { } {
52 # PC31..PC16 are D31..D16, with internal pullups like D15..D0
53 mww 0xfffff870 0xffff0000
55 mww 0xfffff804 0xffff0000
57 # SDRC_CR: set timings
58 mww 0xffffff98 0x2188b0d5
60 # SDRC_MR: issue all banks precharge to SDRAM
64 # SDRC_MR: 8 autorefresh cycles
75 # SDRC_MR: set SDRAM mode registers (CAS, burst len, etc)
79 # SDRC_TR: set refresh rate
83 # SDRC_MR: normal mode, 32 bit bus
88 # The rm9200 chip has just been reset. Bring it up far enough
89 # that we can write flash or run code from SDRAM.
90 proc csb337_reset_init { } {
93 # EBI_CSA: CS0 = NOR, CS1 = SDRAM
99 # Update CP15 control register ... we don't seem to be able to
100 # read/modify/write its value through a TCL variable, so just
101 # write it. Fields are zero unless listed here ... and note
102 # that OpenOCD numbers this register "2", not "1" (!).
104 # - Core to use Async Clocking mode (so it uses 184 MHz most
105 # of the time instead of limiting to the master clock rate):
106 # iA(31) = 1, nF(30) = 1
107 # - Icache on (it's disabled now, slowing i-fetches)
111 arm920t cp15 2 0xc0001078
114 $_TARGETNAME configure -event reset-init {csb337_reset_init}
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