tcl/board/eir.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 # Elector Internet Radio board
   4 # http://www.ethernut.de/en/hardware/eir/index.html
   5
   6 source [find target/at91sam7se512.cfg]
   7
   8 $_TARGETNAME configure -event reset-init {
   9         # WDT_MR, disable watchdog
  10         mww 0xFFFFFD44 0x00008000
  11
  12         # RSTC_MR, enable user reset
  13         mww 0xfffffd08 0xa5000001
  14
  15         # CKGR_MOR
  16         mww 0xFFFFFC20 0x00000601
  17         sleep 10
  18
  19         # CKGR_PLLR
  20         mww 0xFFFFFC2C 0x00481c0e
  21         sleep 10
  22
  23         # PMC_MCKR
  24         mww 0xFFFFFC30 0x00000007
  25         sleep 10
  26
  27         # PMC_IER
  28         mww 0xFFFFFF60 0x00480100
  29
  30         #
  31         # Enable SDRAM interface.
  32         #
  33
  34         # Enable SDRAM control at PIO A.
  35         mww 0xfffff474 0x3f800000 ;# PIO_BSR_OFF
  36         mww 0xfffff404 0x3f800000 ;# PIO_PDR_OFF
  37
  38         # Enable address bus (A0, A2-A11, A13-A17) at PIO B
  39         mww 0xfffff674 0x0003effd ;# PIO_BSR_OFF
  40         mww 0xfffff604 0x0003effd ;# PIO_PDR_OFF
  41
  42         # Enable 16 bit data bus at PIO C
  43         mww 0xfffff870 0x0000ffff ;# PIO_ASR_OFF
  44         mww 0xfffff804 0x0000ffff ;# PIO_PDR_OFF
  45
  46         # Enable SDRAM chip select
  47         mww 0xffffff80 0x00000002 ;# EBI_CSA_OFF
  48
  49         # Set SDRAM characteristics in configuration register.
  50         # Hard coded values for MT48LC32M16A2 with 48MHz CPU.
  51         mww 0xffffffb8 0x2192215a ;# SDRAMC_CR_OFF
  52         sleep 10
  53
  54         # Issue 16 bit SDRAM command: NOP
  55         mww 0xffffffb0 0x00000011 ;# SDRAMC_MR_OFF
  56         mww 0x20000000 0x00000000
  57
  58         # Issue 16 bit SDRAM command: Precharge all
  59         mww 0xffffffb0 0x00000012 ;# SDRAMC_MR_OFF
  60         mww 0x20000000 0x00000000
  61
  62         # Issue 8 auto-refresh cycles
  63         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  64         mww 0x20000000 0x00000000
  65         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  66         mww 0x20000000 0x00000000
  67         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  68         mww 0x20000000 0x00000000
  69         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  70         mww 0x20000000 0x00000000
  71         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  72         mww 0x20000000 0x00000000
  73         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  74         mww 0x20000000 0x00000000
  75         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  76         mww 0x20000000 0x00000000
  77         mww 0xffffffb0 0x00000014 ;# SDRAMC_MR_OFF
  78         mww 0x20000000 0x00000000
  79
  80         # Issue 16 bit SDRAM command: Set mode register
  81         mww 0xffffffb0 0x00000013 ;# SDRAMC_MR_OFF
  82         mww 0x20000014 0xcafedede
  83
  84         # Set refresh rate count ???
  85         mww 0xffffffb4 0x00000013 ;# SDRAMC_TR_OFF
  86
  87         # Issue 16 bit SDRAM command: Normal mode
  88         mww 0xffffffb0 0x00000010 ;# SDRAMC_MR_OFF
  89         mww 0x20000000 0x00000180
  90
  91         #
  92         # Enable external reset key.
  93         #
  94         mww 0xfffffd08 0xa5000001
  95 }