tcl/board/topas910.cfg

   1 # SPDX-License-Identifier: GPL-2.0-or-later
   2
   3 ######################################
   4 # Target:    Toshiba TOPAS910 -- TMPA910 Starterkit
   5 #
   6 ######################################
   7
   8 # We add to the minimal configuration.
   9 source [find target/tmpa910.cfg]
  10
  11 ######################
  12 # Target configuration
  13 ######################
  14
  15 #$_TARGETNAME configure -event gdb-attach { reset init }
  16 $_TARGETNAME configure -event reset-init { topas910_init }
  17
  18 proc topas910_init { } {
  19 # Init PLL
  20 # my settings
  21         mww 0xf005000c 0x00000007
  22         mww 0xf0050010 0x00000065
  23         mww 0xf005000c 0x000000a7
  24         sleep 10
  25         mdw 0xf0050008
  26         mww 0xf0050008 0x00000002
  27         mww 0xf0050004 0x00000000
  28 # NEW: set CLKCR5
  29         mww 0xf0050054 0x00000040
  30 #
  31         sleep 10
  32 # Init SDRAM
  33 #  _PMCDRV          = 0x00000071;
  34 #  //
  35 #  // Initialize SDRAM timing parameter
  36 #  //
  37 #  _DMC_CAS_LATENCY = 0x00000006;
  38 #  _DMC_T_DQSS      = 0x00000000;
  39 #  _DMC_T_MRD       = 0x00000002;
  40 #  _DMC_T_RAS       = 0x00000007;
  41 #
  42 #  _DMC_T_RC        = 0x0000000A;
  43 #  _DMC_T_RCD       = 0x00000013;
  44 #
  45 #  _DMC_T_RFC       = 0x0000010A;
  46 #
  47 #  _DMC_T_RP        = 0x00000013;
  48 #  _DMC_T_RRD       = 0x00000002;
  49 #  _DMC_T_WR        = 0x00000002;
  50 #  _DMC_T_WTR       = 0x00000001;
  51 #  _DMC_T_XP        = 0x0000000A;
  52 #  _DMC_T_XSR       = 0x0000000B;
  53 #  _DMC_T_ESR       = 0x00000014;
  54 #
  55 #  //
  56 #  // Configure SDRAM type parameter
  57 #  _DMC_MEMORY_CFG  = 0x00008011;
  58 #  _DMC_USER_CONFIG = 0x00000011;
  59 #  // 32 bit memory interface
  60 #
  61 #
  62 #  _DMC_REFRESH_PRD = 0x00000A60;
  63 #  _DMC_CHIP_0_CFG  = 0x000140FC;
  64 #
  65 #  _DMC_DIRECT_CMD  = 0x000C0000;
  66 #  _DMC_DIRECT_CMD  = 0x00000000;
  67 #
  68 #  _DMC_DIRECT_CMD  = 0x00040000;
  69 #  _DMC_DIRECT_CMD  = 0x00040000;
  70 #  _DMC_DIRECT_CMD  = 0x00080031;
  71 #  //
  72 #  // Finally start SDRAM
  73 #  //
  74 #  _DMC_MEMC_CMD    = MEMC_CMD_GO;
  75 #  */
  76
  77         mww 0xf0020260 0x00000071
  78         mww 0xf4300014 0x00000006
  79         mww 0xf4300018 0x00000000
  80         mww 0xf430001C 0x00000002
  81         mww 0xf4300020 0x00000007
  82         mww 0xf4300024 0x0000000A
  83         mww 0xf4300028 0x00000013
  84         mww 0xf430002C 0x0000010A
  85         mww 0xf4300030 0x00000013
  86         mww 0xf4300034 0x00000002
  87         mww 0xf4300038 0x00000002
  88         mww 0xf430003C 0x00000001
  89         mww 0xf4300040 0x0000000A
  90         mww 0xf4300044 0x0000000B
  91         mww 0xf4300048 0x00000014
  92         mww 0xf430000C 0x00008011
  93         mww 0xf4300304 0x00000011
  94         mww 0xf4300010 0x00000A60
  95         mww 0xf4300200 0x000140FC
  96         mww 0xf4300008 0x000C0000
  97         mww 0xf4300008 0x00000000
  98         mww 0xf4300008 0x00040000
  99         mww 0xf4300008 0x00040000
 100         mww 0xf4300008 0x00080031
 101         mww 0xf4300004 0x00000000
 102
 103         sleep 10
 104 #       adapter speed NNNN
 105
 106 # remap off in case of IROM boot
 107         mww 0xf0000004 0x00000001
 108
 109 }
 110
 111 # comment the following out if usinf J-Link, it soes not support DCC
 112 arm7_9 dcc_downloads enable       ;# Enable faster DCC downloads
 113
 114
 115 #####################
 116 # Flash configuration
 117 #####################
 118
 119 #flash bank <name> cfi <base> <size> <chip width> <bus width> <target>
 120 set _FLASHNAME $_CHIPNAME.flash
 121 flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 $_TARGETNAME