2 # Configuration script for Arm CoreLink SSE-200 Subsystem based IoT SoCs.
8 swj_newdap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
9 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
12 # SRAM on ARM CoreLink SSE-200 can be 4 banks of 8/16/32/64 KB
13 # We will configure work area assuming 8-KB bank size in SRAM bank 1.
14 # Also SRAM start addresses defaults to secure mode alias.
15 # These values can be overridden as per board configuration
18 global _WORKAREASIZE_CPU0
19 if { [info exists WORKAREASIZE_CPU0] } {
20 set _WORKAREASIZE_CPU0 $WORKAREASIZE_CPU0
22 set _WORKAREASIZE_CPU0 0x1000
25 global _WORKAREAADDR_CPU0
26 if { [info exists WORKAREAADDR_CPU0] } {
27 set _WORKAREAADDR_CPU0 $WORKAREAADDR_CPU0
29 set _WORKAREAADDR_CPU0 0x30008000
33 # Target configuration for Cortex M33 Core 0 on ARM CoreLink SSE-200
34 # Core 0 is the boot core and will always be configured.
37 target create ${TARGET}.CPU0 cortex_m -dap $_CHIPNAME.dap -ap-num 1 -coreid 0
39 ${TARGET}.CPU0 configure -work-area-phys $_WORKAREAADDR_CPU0 -work-area-size $_WORKAREASIZE_CPU0 -work-area-backup 0
41 ${TARGET}.CPU0 cortex_m reset_config sysresetreq
44 # Target configuration for Cortex M33 Core 1 on ARM CoreLink SSE-200
45 # Core 1 is optional and locked at boot until core 0 unlocks it.
48 if { $_ENABLE_CPU1 } {
49 global _WORKAREASIZE_CPU1
50 if { [info exists WORKAREASIZE_CPU1] } {
51 set _WORKAREASIZE_CPU1 $WORKAREASIZE_CPU1
53 set _WORKAREASIZE_CPU1 0x1000
56 global _WORKAREAADDR_CPU1
57 if { [info exists WORKAREAADDR_CPU1] } {
58 set _WORKAREAADDR_CPU1 $WORKAREAADDR_CPU1
60 set _WORKAREAADDR_CPU1 0x30009000
63 target create ${TARGET}.CPU1 cortex_m -dap $_CHIPNAME.dap -ap-num 2 -coreid 1
65 ${TARGET}.CPU1 configure -work-area-phys $_WORKAREAADDR_CPU1 -work-area-size $_WORKAREASIZE_CPU1 -work-area-backup 0
67 ${TARGET}.CPU1 cortex_m reset_config vectreset
70 # Make sure the default target is the boot core
71 targets ${TARGET}.CPU0
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