2 # configuration file for NXP i.MX8M family of SoCs
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
10 if { [info exists CHIPCORES] } {
16 # CoreSight Debug Access Port
17 if { [info exists DAP_TAPID] } {
18 set _DAP_TAPID $DAP_TAPID
20 set _DAP_TAPID 0x5ba00477
24 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x01 -irmask 0x0f \
25 -expected-id $_DAP_TAPID
27 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
29 set _TARGETNAME $_CHIPNAME.a53
30 set _CTINAME $_CHIPNAME.cti
32 set DBGBASE {0x80410000 0x80510000 0x80610000 0x80710000}
33 set CTIBASE {0x80420000 0x80520000 0x80620000 0x80720000}
35 for { set _core 0 } { $_core < $_cores } { incr _core } {
37 cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
38 -baseaddr [lindex $CTIBASE $_core]
40 set _command "target create $_TARGETNAME.$_core aarch64 -dap $_CHIPNAME.dap \
41 -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core"
44 # non-boot core examination may fail
45 set _command "$_command -defer-examine"
46 set _smp_command "$_smp_command $_TARGETNAME.$_core"
48 set _smp_command "target smp $_TARGETNAME.$_core"
56 # declare the auxiliary Cortex-M4 core on AP #4
57 target create ${_CHIPNAME}.m4 cortex_m -dap ${_CHIPNAME}.dap -ap-num 4 \
60 # AHB-AP for direct access to soc bus
61 target create ${_CHIPNAME}.ahb mem_ap -dap ${_CHIPNAME}.dap -ap-num 0
63 # default target is A53 core 0
64 targets $_TARGETNAME.0
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