1 # SPDX-License-Identifier: GPL-2.0-or-later
3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 if { [info exists CPUTAPID] } {
10 set _CPUTAPID $CPUTAPID
12 set _CPUTAPID 0x0596802B
15 if { [info exists HAS_ETB] } {
17 # Set default (no ETB).
18 # Show a warning, because this should have been configured explicitly.
23 if { [info exists ETBTAPID] } {
24 set _ETBTAPID $ETBTAPID
26 set _ETBTAPID 0x1B900F0F
29 # TRST and SRST both exist, and can be controlled independently
30 reset_config trst_and_srst separate
32 # Define the _TARGETNAME
33 set _TARGETNAME $_CHIPNAME.cpu
35 # Include the ETB tap controller if asked for.
36 # Has to be done manually for newer devices (not an "old" LPC2917/2919).
37 if { $HAS_ETB == 1 } {
38 # Clear the HAS_ETB flag. Must be set again for a new tap in the chain.
41 # Add the ETB tap controller and the ARM9 core debug tap
42 jtag newtap $_CHIPNAME etb -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_ETBTAPID
43 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
45 # Create the ".cpu" target
46 target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
48 # Configure ETM and ETB
49 etm config $_TARGETNAME 8 normal full etb
50 etb config $_TARGETNAME $_CHIPNAME.etb
53 # Add the ARM9 core debug tap
54 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
56 # Create the ".cpu" target
57 target create $_TARGETNAME arm966e -endian little -chain-position $_TARGETNAME
61 arm7_9 dcc_downloads enable
63 # Flash bank configuration:
64 # Flash: flash bank lpc2900 0 0 0 0 <target#> <flash clock (CLK_SYS_FMC) in kHz>
65 # Flash base address, total flash size, and number of sectors are all configured automatically.
66 set _FLASHNAME $_CHIPNAME.flash
67 flash bank $_FLASHNAME lpc2900 0 0 0 0 $_TARGETNAME $FLASH_CLOCK
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