4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
13 if { [info exists M4_JTAG_TAPID] } {
14 set _M4_JTAG_TAPID $M4_JTAG_TAPID
16 set _M4_JTAG_TAPID 0x4ba00477
22 if { [info exists M4_SWD_TAPID] } {
23 set _M4_SWD_TAPID $M4_SWD_TAPID
25 set _M4_SWD_TAPID 0x2ba01477
31 if { [info exists M0_JTAG_TAPID] } {
32 set _M0_JTAG_TAPID $M0_JTAG_TAPID
34 set _M0_JTAG_TAPID 0x0ba01477
37 jtag newtap $_CHIPNAME m4 -irlen 4 -ircapture 0x1 -irmask 0xf \
38 -expected-id $_M4_JTAG_TAPID
40 jtag newtap $_CHIPNAME m0 -irlen 4 -ircapture 0x1 -irmask 0xf \
41 -expected-id $_M0_JTAG_TAPID
43 target create $_CHIPNAME.m4 cortex_m3 -chain-position $_CHIPNAME.m4
44 target create $_CHIPNAME.m0 cortex_m3 -chain-position $_CHIPNAME.m0
46 # on this CPU we should use VECTRESET to perform a soft reset and
47 # manually reset the periphery
48 # SRST or SYSRESETREQ disable the debug interface for the time of
49 # the reset and will not fit our requirements for a consistent debug
51 cortex_m3 reset_config vectreset
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