2 # script for Nordic nRF51 series, a CORTEX-M0 chip
5 source [find target/swj-dp.tcl]
7 if { [info exists CHIPNAME] } {
8 set _CHIPNAME $CHIPNAME
13 if { [info exists ENDIAN] } {
19 # Work-area is a space in RAM used for flash programming
21 if { [info exists WORKAREASIZE] } {
22 set _WORKAREASIZE $WORKAREASIZE
24 set _WORKAREASIZE 0x800
27 if { [info exists CPUTAPID] } {
28 set _CPUTAPID $CPUTAPID
30 set _CPUTAPID 0x0bb11477
33 swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
35 set _TARGETNAME $_CHIPNAME.cpu
36 target create $_TARGETNAME cortex_m -chain-position $_TARGETNAME
38 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
41 # The chip supports standard ARM/Cortex-M0 SYSRESETREQ signal
42 cortex_m reset_config sysresetreq
45 flash bank $_CHIPNAME.flash nrf51 0x00000000 0 1 1 $_TARGETNAME
46 flash bank $_CHIPNAME.uicr nrf51 0x10001000 0 1 1 $_TARGETNAME
49 # The chip should start up from internal 16Mhz RC, so setting adapter
50 # clock to 1Mhz should be OK
54 proc enable_all_ram {} {
55 # nRF51822 Product Anomaly Notice (PAN) #16 explains that not all RAM banks
56 # are reliably enabled after reset on some revisions (contrary to spec.) So after
57 # resetting we enable all banks via the RAMON register
60 $_TARGETNAME configure -event reset-end { enable_all_ram }
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