1 # SPDX-License-Identifier: GPL-2.0-or-later
3 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
4 # This chip is now at end-of-life. Final orders have been taken.
6 if { [info exists CHIPNAME] } {
7 set _CHIPNAME $CHIPNAME
12 if { [info exists ENDIAN] } {
18 if { [info exists CPUTAPID] } {
19 set _CPUTAPID $CPUTAPID
21 set _CPUTAPID 0x69264013
24 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
26 set _TARGETNAME $_CHIPNAME.cpu
27 target create $_TARGETNAME xscale -endian $_ENDIAN \
28 -chain-position $_CHIPNAME.cpu
30 # PXA255 comes out of reset using 3.6864 MHz oscillator.
31 # Until the PLL kicks in, keep the JTAG clock slow enough
32 # that we get no errors.
34 $_TARGETNAME configure -event "reset-start" { adapter speed 300 }
36 # both TRST and SRST are *required* for debug
37 # DCSR is often accessed with SRST active
38 reset_config trst_and_srst separate srst_nogate
40 # reset processing that works with PXA
41 proc init_reset {mode} {
42 # assert both resets; equivalent to power-on reset
43 adapter assert trst assert srst
45 # drop TRST after at least 32 cycles
47 adapter deassert trst assert srst
49 # minimum 32 TCK cycles to wake up the controller
52 # now the TAP will be responsive; validate scanchain
55 # ... and take it out of reset
56 adapter deassert trst deassert srst
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