1 # PXA255 chip ... originally from Intel, PXA line was sold to Marvell.
2 # This chip is now at end-of-life. Final orders have been taken.
4 if { [info exists CHIPNAME] } {
5 set _CHIPNAME $CHIPNAME
10 if { [info exists ENDIAN] } {
16 if { [info exists CPUTAPID] } {
17 set _CPUTAPID $CPUTAPID
19 set _CPUTAPID 0x69264013
22 jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id $_CPUTAPID
24 set _TARGETNAME $_CHIPNAME.cpu
25 target create $_TARGETNAME xscale -endian $_ENDIAN \
26 -chain-position $_CHIPNAME.cpu
28 # PXA255 comes out of reset using 3.6864 MHz oscillator.
29 # Until the PLL kicks in, keep the JTAG clock slow enough
30 # that we get no errors.
32 $_TARGETNAME configure -event "reset-start" { adapter_khz 300 }
34 # both TRST and SRST are *required* for debug
35 # DCSR is often accessed with SRST active
36 reset_config trst_and_srst separate srst_nogate
38 # reset processing that works with PXA
39 proc init_reset {mode} {
40 # assert both resets; equivalent to power-on reset
43 # drop TRST after at least 32 cycles
47 # minimum 32 TCK cycles to wake up the controller
50 # now the TAP will be responsive; validate scanchain
53 # ... and take it out of reset
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