1 # script for stm32g0x family
4 # stm32g0 devices support SWD transports only.
6 source [find target/swj-dp.tcl]
7 source [find mem_helper.tcl]
9 if { [info exists CHIPNAME] } {
10 set _CHIPNAME $CHIPNAME
12 set _CHIPNAME stm32g0x
17 # Work-area is a space in RAM used for flash programming
18 # Smallest proposed target has 8kB ram, use 4kB by default to avoid surprises
19 if { [info exists WORKAREASIZE] } {
20 set _WORKAREASIZE $WORKAREASIZE
22 set _WORKAREASIZE 0x1000
26 if { [info exists CPUTAPID] } {
27 set _CPUTAPID $CPUTAPID
29 # Section 37.5.5 - corresponds to Cortex-M0+
30 set _CPUTAPID 0x0bc11477
33 swj_newdap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
34 dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
36 set _TARGETNAME $_CHIPNAME.cpu
37 target create $_TARGETNAME cortex_m -endian $_ENDIAN -dap $_CHIPNAME.dap
39 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
41 flash bank $_CHIPNAME.flash stm32l4x 0x08000000 0 0 0 $_TARGETNAME
42 flash bank $_CHIPNAME.otp stm32l4x 0x1fff7000 0 0 0 $_TARGETNAME
47 adapter srst delay 100
52 reset_config srst_nogate
55 # if srst is not fitted use SYSRESETREQ to
56 # perform a soft reset
57 cortex_m reset_config sysresetreq
60 proc stm32g0x_default_reset_start {} {
61 # Reset clock is HSI16 (16 MHz)
65 proc stm32g0x_default_examine_end {} {
66 # DBGMCU_CR |= DBG_STANDBY | DBG_STOP
67 mmw 0x40015804 0x00000006 0
69 # Stop watchdog counters during halt
70 # DBGMCU_APB1_FZ |= DBG_IWDG_STOP | DBG_WWDG_STOP
71 mmw 0x40015808 0x00001800 0
74 proc stm32g0x_default_reset_init {} {
75 # Increase clock to 64 Mhz
76 mmw 0x40022000 0x00000002 0x00000005 ;# FLASH_ACR: Latency = 2
77 mww 0x4002100C 0x30000802 ;# RCC_PLLCFGR = PLLR=/2, PLLN=8, PLLM=/1, PLLSRC=0x2
78 mmw 0x40021000 0x01000000 0x00000000 ;# RCC_CR |= PLLON
79 mmw 0x40021008 0x00000002 0x00000005 ;# RCC_CFGR: SW=PLLRCLK
81 # Boost JTAG frequency
86 $_TARGETNAME configure -event examine-end { stm32g0x_default_examine_end }
87 $_TARGETNAME configure -event reset-start { stm32g0x_default_reset_start }
88 $_TARGETNAME configure -event reset-init { stm32g0x_default_reset_init }
Linking to existing account procedure
If you already have an account and want to add another login method
you
MUST first sign in with your existing account and
then change URL to read
https://review.openocd.org/login/?link
to get to this page again but this time it'll work for linking. Thank you.
SSH host keys fingerprints
1024 SHA256:YKx8b7u5ZWdcbp7/4AeXNaqElP49m6QrwfXaqQGJAOk gerrit-code-review@openocd.zylin.com (DSA)
384 SHA256:jHIbSQa4REvwCFG4cq5LBlBLxmxSqelQPem/EXIrxjk gerrit-code-review@openocd.org (ECDSA)
521 SHA256:UAOPYkU9Fjtcao0Ul/Rrlnj/OsQvt+pgdYSZ4jOYdgs gerrit-code-review@openocd.org (ECDSA)
256 SHA256:A13M5QlnozFOvTllybRZH6vm7iSt0XLxbA48yfc2yfY gerrit-code-review@openocd.org (ECDSA)
256 SHA256:spYMBqEYoAOtK7yZBrcwE8ZpYt6b68Cfh9yEVetvbXg gerrit-code-review@openocd.org (ED25519)
+--[ED25519 256]--+
|=.. |
|+o.. . |
|*.o . . |
|+B . . . |
|Bo. = o S |
|Oo.+ + = |
|oB=.* = . o |
| =+=.+ + E |
|. .=o . o |
+----[SHA256]-----+
2048 SHA256:0Onrb7/PHjpo6iVZ7xQX2riKN83FJ3KGU0TvI0TaFG4 gerrit-code-review@openocd.zylin.com (RSA)