3 if { [info exists CHIPNAME] } {
4 set _CHIPNAME $CHIPNAME
9 if { [info exists ENDIAN] } {
15 # Work-area is a space in RAM used for flash programming
17 if { [info exists WORKAREASIZE] } {
18 set _WORKAREASIZE $WORKAREASIZE
20 set _WORKAREASIZE 0x3800
23 # JTAG speed should be <= F_CPU/6.
24 # F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
27 adapter_nsrst_delay 100
31 if { [info exists CPUTAPID] } {
32 set _CPUTAPID $CPUTAPID
34 # See STM Document RM0038
36 set _CPUTAPID 0x4ba00477
38 jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
40 if { [info exists BSTAPID] } {
41 # FIXME this never gets used to override defaults...
44 # See STM Document RM0038
46 set _BSTAPID 0x06416041
48 jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
50 set _TARGETNAME $_CHIPNAME.cpu
51 target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
53 $_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
56 # flash size will be probed
57 set _FLASHNAME $_CHIPNAME.flash
58 flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
60 # if srst is not fitted use SYSRESETREQ to
61 # perform a soft reset
62 cortex_m3 reset_config sysresetreq
64 proc stm32l_enable_HSI {} {
65 # Enable HSI as clock source
66 echo "STM32L: Enabling HSI"
69 mww 0x40023800 0x00000101
72 mww 0x40023808 0x00000001
78 $_TARGETNAME configure -event reset-init {
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