*/
if (arm->cpsr) {
buf_set_u32(arm->cpsr->value, 0, 32, cpsr);
- arm->cpsr->valid = 1;
- arm->cpsr->dirty = 0;
+ arm->cpsr->valid = true;
+ arm->cpsr->dirty = false;
}
arm->core_mode = mode;
struct reg arm_gdb_dummy_fp_reg = {
.name = "GDB dummy FPA register",
.value = (uint8_t *) arm_gdb_dummy_fp_value,
- .valid = 1,
+ .valid = true,
.size = 96,
.exist = false,
.number = 16,
struct reg arm_gdb_dummy_fps_reg = {
.name = "GDB dummy FPA status register",
.value = (uint8_t *) arm_gdb_dummy_fps_value,
- .valid = 1,
+ .valid = true,
.size = 32,
.exist = false,
.number = 24,
retval = reg_arch_info->arm->read_core_reg(target, reg,
reg_arch_info->num, reg_arch_info->mode);
if (retval == ERROR_OK) {
- reg->valid = 1;
- reg->dirty = 0;
+ reg->valid = true;
+ reg->dirty = false;
}
return retval;
value = buf_get_u32(buf + 4, 0, 32);
buf_set_u32(reg->value + 4, 0, 32, value);
}
- reg->valid = 1;
+ reg->valid = true;
}
- reg->dirty = 1;
+ reg->dirty = true;
return ERROR_OK;
}
cpsr = buf_get_u32(arm->cpsr->value, 0, 32);
for (i = 0; i < num_mem_params; i++) {
+ if (mem_params[i].direction == PARAM_IN)
+ continue;
retval = target_write_buffer(target, mem_params[i].address, mem_params[i].size,
mem_params[i].value);
if (retval != ERROR_OK)
arm_algorithm_info->core_mode);
buf_set_u32(arm->cpsr->value, 0, 5,
arm_algorithm_info->core_mode);
- arm->cpsr->dirty = 1;
- arm->cpsr->valid = 1;
+ arm->cpsr->dirty = true;
+ arm->cpsr->valid = true;
}
/* terminate using a hardware or (ARMv5+) software breakpoint */
buf_set_u32(ARMV4_5_CORE_REG_MODE(arm->core_cache,
arm_algorithm_info->core_mode, i).value, 0, 32, context[i]);
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
- i).valid = 1;
+ i).valid = true;
ARMV4_5_CORE_REG_MODE(arm->core_cache, arm_algorithm_info->core_mode,
- i).dirty = 1;
+ i).dirty = true;
}
}
arm_set_cpsr(arm, cpsr);
- arm->cpsr->dirty = 1;
+ arm->cpsr->dirty = true;
arm->core_state = core_state;