* Copyright (C) 2008 by Gheorghe Guran (atlas) *
* *
* This program is free software; you can redistribute it and/or modify *
* Copyright (C) 2008 by Gheorghe Guran (atlas) *
* *
* This program is free software; you can redistribute it and/or modify *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
- * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the *
- * GNU General public License for more details. *
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
+ * GNU General Public License for more details. *
- * You should have received a copy of the GNU General public License *
- * along with this program; if not, write to the *
- * Free Software Foundation, Inc., *
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
+ * You should have received a copy of the GNU General Public License *
+ * along with this program. If not, see <http://www.gnu.org/licenses/>. *
****************************************************************************/
/***************************************************************************
****************************************************************************/
/***************************************************************************
-#define DBGU_CIDR 0xFFFFF240
-#define CKGR_MCFR 0xFFFFFC24
-#define CKGR_MOR 0xFFFFFC20
-#define CKGR_MCFR_MAINRDY 0x10000
-#define CKGR_PLLR 0xFFFFFC2c
-#define CKGR_PLLR_DIV 0xff
-#define CKGR_PLLR_MUL 0x07ff0000
-#define PMC_MCKR 0xFFFFFC30
-#define PMC_MCKR_CSS 0x03
-#define PMC_MCKR_PRES 0x1c
+#define DBGU_CIDR 0xFFFFF240
+#define CKGR_MCFR 0xFFFFFC24
+#define CKGR_MOR 0xFFFFFC20
+#define CKGR_MCFR_MAINRDY 0x10000
+#define CKGR_PLLR 0xFFFFFC2c
+#define CKGR_PLLR_DIV 0xff
+#define CKGR_PLLR_MUL 0x07ff0000
+#define PMC_MCKR 0xFFFFFC30
+#define PMC_MCKR_CSS 0x03
+#define PMC_MCKR_PRES 0x1c
-#define FMR_TIMING_NONE 0
-#define FMR_TIMING_NVBITS 1
-#define FMR_TIMING_FLASH 2
+#define FMR_TIMING_NONE 0
+#define FMR_TIMING_NVBITS 1
+#define FMR_TIMING_FLASH 2
-#define FLASH_SIZE_8KB 1
-#define FLASH_SIZE_16KB 2
-#define FLASH_SIZE_32KB 3
-#define FLASH_SIZE_64KB 5
-#define FLASH_SIZE_128KB 7
-#define FLASH_SIZE_256KB 9
-#define FLASH_SIZE_512KB 10
-#define FLASH_SIZE_1024KB 12
-#define FLASH_SIZE_2048KB 14
-
+#define FLASH_SIZE_8KB 1
+#define FLASH_SIZE_16KB 2
+#define FLASH_SIZE_32KB 3
+#define FLASH_SIZE_64KB 5
+#define FLASH_SIZE_128KB 7
+#define FLASH_SIZE_256KB 9
+#define FLASH_SIZE_512KB 10
+#define FLASH_SIZE_1024KB 12
+#define FLASH_SIZE_2048KB 14
-static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count);
+static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset,
+ uint32_t count);
static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
static uint32_t at91sam7_get_flash_status(struct target *target, int bank_number);
static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode);
static uint32_t at91sam7_wait_status_busy(struct flash_bank *bank, uint32_t waitbits, int timeout);
static int at91sam7_flash_command(struct flash_bank *bank, uint8_t cmd, uint16_t pagen);
-static uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
-static uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
-static uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
+static const uint32_t MC_FMR[4] = { 0xFFFFFF60, 0xFFFFFF70, 0xFFFFFF80, 0xFFFFFF90 };
+static const uint32_t MC_FCR[4] = { 0xFFFFFF64, 0xFFFFFF74, 0xFFFFFF84, 0xFFFFFF94 };
+static const uint32_t MC_FSR[4] = { 0xFFFFFF68, 0xFFFFFF78, 0xFFFFFF88, 0xFFFFFF98 };
-static char * EPROC[8]= {"Unknown","ARM946-E","ARM7TDMI","Unknown","ARM920T","ARM926EJ-S","Unknown","Unknown"};
+static const char *EPROC[8] = {
+ "Unknown", "ARM946-E", "ARM7TDMI", "Unknown", "ARM920T", "ARM926EJ-S", "Unknown", "Unknown"
+};
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
target_read_u32(target, CKGR_PLLR, &pllr);
if (!(pllr & CKGR_PLLR_DIV))
at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
/* Integer arithmetic should have sufficient precision
* as long as PLL is properly configured. */
tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
at91sam7_info->mck_valid = 1;
mainfreq = RC_FREQ / 16ul * (mcfr & 0xffff);
/* Integer arithmetic should have sufficient precision
* as long as PLL is properly configured. */
tmp = mainfreq / (pllr & CKGR_PLLR_DIV)*
- (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
- }
- else if ((at91sam7_info->ext_freq != 0) &&
- ((pllr&CKGR_PLLR_DIV) != 0))
- {
+ (((pllr & CKGR_PLLR_MUL) >> 16) + 1);
+ } else if ((at91sam7_info->ext_freq != 0) &&
+ ((pllr&CKGR_PLLR_DIV) != 0)) {
/* main clocks in 1.5uS */
fmcn = (at91sam7_info->mck_freq/1000000ul)+
(at91sam7_info->mck_freq/2000000ul) + 1;
/* main clocks in 1.5uS */
fmcn = (at91sam7_info->mck_freq/1000000ul)+
(at91sam7_info->mck_freq/2000000ul) + 1;
- while ((!((status = at91sam7_get_flash_status(bank->target, bank->bank_number)) & waitbits)) && (timeout-- > 0))
- {
+ while ((!((status = at91sam7_get_flash_status(bank->target,
+ bank->bank_number)) & waitbits)) && (timeout-- > 0)) {
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", (int)bank->bank_number, status);
alive_sleep(1);
}
LOG_DEBUG("status[%i]: 0x%" PRIx32 "", bank->bank_number, status);
LOG_ERROR("status register: 0x%" PRIx32 "", status);
if (status & 0x4)
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
LOG_ERROR("status register: 0x%" PRIx32 "", status);
if (status & 0x4)
LOG_ERROR("Lock Error Bit Detected, Operation Abort");
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
fcr = (0x5A << 24) | ((pagen&0x3FF) << 8) | cmd;
target_write_u32(target, MC_FCR[bank->bank_number], fcr);
- LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u", fcr, bank->bank_number + 1, pagen);
+ LOG_DEBUG("Flash command: 0x%" PRIx32 ", flash bank: %i, page number: %u",
+ fcr,
+ bank->bank_number + 1,
+ pagen);
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
/* Lock bit manipulation on AT91SAM7A3 waits for FC_FSR bit 1, EOL */
if (at91sam7_wait_status_busy(bank, MC_FSR_EOL, 10)&0x0C)
/* Read device id register, main clock frequency register and fill in driver info structure */
static int at91sam7_read_part_info(struct flash_bank *bank)
{
/* Read device id register, main clock frequency register and fill in driver info structure */
static int at91sam7_read_part_info(struct flash_bank *bank)
{
/* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr);
/* Read and parse chip identification register */
target_read_u32(target, DBGU_CIDR, &cidr);
- if (strcmp(target_name_t, "Unknown") == 0)
- {
- LOG_ERROR("Target autodetection failed! Please specify target parameters in configuration file");
+ if (strcmp(target_name_t, "Unknown") == 0) {
+ LOG_ERROR(
+ "Target autodetection failed! Please specify target parameters in configuration file");
- for (bnk = 0; bnk < banks_num; bnk++)
- {
- if (bnk > 0)
- {
- /* create a new flash bank element */
- struct flash_bank *fb = malloc(sizeof(struct flash_bank));
- fb->target = target;
- fb->driver = bank->driver;
- fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
- fb->next = NULL;
-
- /* link created bank in 'flash_banks' list and redirect t_bank */
- t_bank->next = fb;
- t_bank = fb;
+ for (bnk = 0; bnk < banks_num; bnk++) {
+ struct flash_bank *t_bank = bank;
+ if (bnk > 0) {
+ if (!t_bank->next) {
+ /* create a new flash bank element */
+ struct flash_bank *fb = malloc(sizeof(struct flash_bank));
+ fb->target = target;
+ fb->driver = bank->driver;
+ fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
+ fb->name = "sam7_probed";
+ fb->next = NULL;
+
+ /* link created bank in 'flash_banks' list */
+ t_bank->next = fb;
+ }
+ t_bank = t_bank->next;
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
t_bank->sectors[sec].is_erased = -1;
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
t_bank->sectors[sec].is_erased = -1;
- LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x", at91sam7_info->cidr_nvptyp, at91sam7_info->cidr_arch);
+ LOG_DEBUG("nvptyp: 0x%3.3x, arch: 0x%4.4x",
+ at91sam7_info->cidr_nvptyp,
+ at91sam7_info->cidr_arch);
- for (nSector = 0; nSector < bank->num_sectors; nSector++)
- {
- retval = target_blank_check_memory(target, bank->base + bank->sectors[nSector].offset,
- bank->sectors[nSector].size, &blank);
- if (retval != ERROR_OK)
- {
+ for (nSector = 0; nSector < bank->num_sectors; nSector++) {
+ retval = target_blank_check_memory(target,
+ bank->base + bank->sectors[nSector].offset,
+ bank->sectors[nSector].size,
+ &blank, bank->erased_value);
+ if (retval != ERROR_OK) {
LOG_USER("Running slow fallback erase check - add working memory");
buffer = malloc(bank->sectors[0].size);
LOG_USER("Running slow fallback erase check - add working memory");
buffer = malloc(bank->sectors[0].size);
bank->sectors[nSector].is_erased = 1;
retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
bank->sectors[nSector].is_erased = 1;
retval = target_read_memory(target, bank->base + bank->sectors[nSector].offset, 4,
- for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++)
- {
- if (((status >> (16 + lock_pos))&(0x0001)) == 1)
- {
+ for (lock_pos = 0; lock_pos < bank->num_sectors; lock_pos++) {
+ if (((status >> (16 + lock_pos))&(0x0001)) == 1) {
- for (bnk = 0; bnk < banks_num; bnk++)
- {
- if (bnk > 0)
- {
- /* create a new bank element */
- struct flash_bank *fb = malloc(sizeof(struct flash_bank));
- fb->target = target;
- fb->driver = bank->driver;
- fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
- fb->next = NULL;
-
- /* link created bank in 'flash_banks' list and redirect t_bank */
- t_bank->next = fb;
- t_bank = fb;
+ for (bnk = 0; bnk < banks_num; bnk++) {
+ if (bnk > 0) {
+ if (!t_bank->next) {
+ /* create a new bank element */
+ struct flash_bank *fb = malloc(sizeof(struct flash_bank));
+ fb->target = target;
+ fb->driver = bank->driver;
+ fb->driver_priv = malloc(sizeof(struct at91sam7_flash_bank));
+ fb->name = "sam7_probed";
+ fb->next = NULL;
+
+ /* link created bank in 'flash_banks' list */
+ t_bank->next = fb;
+ }
+ t_bank = t_bank->next;
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
t_bank->sectors[sec].is_erased = -1;
t_bank->sectors[sec].offset = sec * pages_per_sector * page_size;
t_bank->sectors[sec].size = pages_per_sector * page_size;
t_bank->sectors[sec].is_erased = -1;
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
/* allocate and clean buffer */
nbytes = (last - first + 1) * bank->sectors[first].size;
buffer = malloc(nbytes * sizeof(uint8_t));
for (pos = 0; pos < nbytes; pos++)
/* allocate and clean buffer */
nbytes = (last - first + 1) * bank->sectors[first].size;
buffer = malloc(nbytes * sizeof(uint8_t));
for (pos = 0; pos < nbytes; pos++)
- if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK)
- {
+ if (at91sam7_write(bank, buffer, bank->sectors[first].offset, nbytes) != ERROR_OK) {
+ free(buffer);
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
LOG_ERROR("Target not halted");
return ERROR_TARGET_NOT_HALTED;
}
if ((first < 0) || (last < first) || (last >= bank->num_sectors))
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
pagen = sector * at91sam7_info->pages_per_sector;
if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
pagen = sector * at91sam7_info->pages_per_sector;
if (at91sam7_flash_command(bank, cmd, pagen) != ERROR_OK)
-static int at91sam7_write(struct flash_bank *bank, uint8_t *buffer, uint32_t offset, uint32_t count)
+static int at91sam7_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t offset, uint32_t count)
uint32_t first_page, last_page, pagen, buffer_pos;
if (at91sam7_info->cidr == 0)
uint32_t first_page, last_page, pagen, buffer_pos;
if (at91sam7_info->cidr == 0)
- if (offset % dst_min_alignment)
- {
- LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "", offset, dst_min_alignment);
+ if (offset % dst_min_alignment) {
+ LOG_WARNING("offset 0x%" PRIx32 " breaks required alignment 0x%" PRIx32 "",
+ offset,
+ dst_min_alignment);
first_page = offset/dst_min_alignment;
last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
first_page = offset/dst_min_alignment;
last_page = DIV_ROUND_UP(offset + count, dst_min_alignment);
- LOG_DEBUG("first_page: %i, last_page: %i, count %i", (int)first_page, (int)last_page, (int)count);
+ LOG_DEBUG("first_page: %i, last_page: %i, count %i",
+ (int)first_page,
+ (int)last_page,
+ (int)count);
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
/* Configure the flash controller timing */
at91sam7_read_clock_info(bank);
at91sam7_set_flash_mode(bank, FMR_TIMING_FLASH);
- wcount = DIV_ROUND_UP(count,4);
- if ((retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4, wcount, buffer + buffer_pos)) != ERROR_OK)
- {
+ wcount = DIV_ROUND_UP(count, 4);
+ retval = target_write_memory(target, bank->base + pagen*dst_min_alignment, 4,
+ wcount, buffer + buffer_pos);
+ if (retval != ERROR_OK)
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
/* Send Write Page command to Flash Controller */
if (at91sam7_flash_command(bank, WP, pagen) != ERROR_OK)
- "\n at91sam7 driver information: Chip is %s\n",
- at91sam7_info->target_name);
+ "\n at91sam7 driver information: Chip is %s\n",
+ at91sam7_info->target_name);
- buf_size,
- " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | Flashsize: 0x%8.8" PRIx32 "\n",
- at91sam7_info->cidr,
- at91sam7_info->cidr_arch,
- EPROC[at91sam7_info->cidr_eproc],
- at91sam7_info->cidr_version,
- bank->size);
+ buf_size,
+ " Cidr: 0x%8.8" PRIx32 " | Arch: 0x%4.4x | Eproc: %s | Version: 0x%3.3x | "
+ "Flashsize: 0x%8.8" PRIx32 "\n",
+ at91sam7_info->cidr,
+ at91sam7_info->cidr_arch,
+ EPROC[at91sam7_info->cidr_eproc],
+ at91sam7_info->cidr_version,
+ bank->size);
- " Master clock (estimated): %u KHz | External clock: %u KHz\n",
- (unsigned)(at91sam7_info->mck_freq / 1000), (unsigned)(at91sam7_info->ext_freq / 1000));
+ " Master clock (estimated): %u KHz | External clock: %u KHz\n",
+ (unsigned)(at91sam7_info->mck_freq / 1000),
+ (unsigned)(at91sam7_info->ext_freq / 1000));
- printed = snprintf(buf, buf_size,
- " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i \n",
- at91sam7_info->pagesize, bank->num_sectors, at91sam7_info->num_lockbits_on,
- at91sam7_info->lockbits, at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
+ printed = snprintf(buf,
+ buf_size,
+ " Pagesize: %i bytes | Lockbits(%i): %i 0x%4.4x | Pages in lock region: %i\n",
+ at91sam7_info->pagesize,
+ bank->num_sectors,
+ at91sam7_info->num_lockbits_on,
+ at91sam7_info->lockbits,
+ at91sam7_info->pages_per_sector*at91sam7_info->num_lockbits_on);
command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
return ERROR_FLASH_BANK_INVALID;
}
command_print(CMD_CTX, "not an at91sam7 flash bank '%s'", CMD_ARGV[0]);
return ERROR_FLASH_BANK_INVALID;
}
LOG_ERROR("target has to be halted to perform flash operation");
return ERROR_TARGET_NOT_HALTED;
}
if (strcmp(CMD_ARGV[1], "set") == 0)
LOG_ERROR("target has to be halted to perform flash operation");
return ERROR_TARGET_NOT_HALTED;
}
if (strcmp(CMD_ARGV[1], "set") == 0)
- if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits))
- {
- command_print(CMD_CTX, "gpnvm bit '#%s' is out of bounds for target %s", CMD_ARGV[0], at91sam7_info->target_name);
+ if ((bit < 0) || (bit >= at91sam7_info->num_nvmbits)) {
+ command_print(CMD_CTX,
+ "gpnvm bit '#%s' is out of bounds for target %s",
+ CMD_ARGV[0],
+ at91sam7_info->target_name);
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
at91sam7_set_flash_mode(bank, FMR_TIMING_NVBITS);
if (at91sam7_flash_command(bank, flashcmd, bit) != ERROR_OK)
/* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
status = at91sam7_get_flash_status(bank->target, 0);
/* GPNVM and SECURITY bits apply only for MC_FSR of EFC0 */
status = at91sam7_get_flash_status(bank->target, 0);
- LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32, flashcmd, bit, status);
+ LOG_DEBUG("at91sam7_handle_gpnvm_command: cmd 0x%x, value %d, status 0x%" PRIx32,
+ flashcmd,
+ bit,
+ status);
.chain = at91sam7_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
.chain = at91sam7_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
.commands = at91sam7_command_handlers,
.flash_bank_command = at91sam7_flash_bank_command,
.erase = at91sam7_erase,
.commands = at91sam7_command_handlers,
.flash_bank_command = at91sam7_flash_bank_command,
.erase = at91sam7_erase,