+ if (k_bank->prog_base == 0 && !allow_fcf_writes) {
+ if (bank->sectors[1].offset <= FCF_ADDRESS)
+ sect = 1; /* 1kb sector, FCF in 2nd sector */
+
+ if (offset < bank->sectors[sect].offset + bank->sectors[sect].size
+ && offset + count > bank->sectors[sect].offset)
+ set_fcf = true; /* write to any part of sector with FCF */
+ }
+
+ if (set_fcf) {
+ kinetis_fill_fcf(bank, fcf_buffer);
+
+ fcf_in_data_valid = offset <= FCF_ADDRESS
+ && offset + count >= FCF_ADDRESS + FCF_SIZE;
+ if (fcf_in_data_valid) {
+ memcpy(fcf_in_data, buffer + FCF_ADDRESS - offset, FCF_SIZE);
+ if (memcmp(fcf_in_data, fcf_buffer, 8)) {
+ fcf_differs = true;
+ LOG_INFO("Setting of backdoor key is not supported in mode 'kinetis fcf_source protection'.");
+ }
+ if (memcmp(fcf_in_data + FCF_FPROT, fcf_buffer + FCF_FPROT, 4)) {
+ fcf_differs = true;
+ LOG_INFO("Flash protection requested in the programmed file differs from current setting.");
+ }
+ if (fcf_in_data[FCF_FDPROT] != fcf_buffer[FCF_FDPROT]) {
+ fcf_differs = true;
+ LOG_INFO("Data flash protection requested in the programmed file differs from current setting.");
+ }
+ if ((fcf_in_data[FCF_FSEC] & 3) != 2) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Device security requested in the programmed file! Write denied.");
+ } else if (fcf_in_data[FCF_FSEC] != fcf_buffer[FCF_FSEC]) {
+ fcf_differs = true;
+ LOG_INFO("Strange unsecure mode 0x%02" PRIx8
+ " requested in the programmed file, set FSEC = 0x%02" PRIx8
+ " in the startup code!",
+ fcf_in_data[FCF_FSEC], fcf_buffer[FCF_FSEC]);
+ }
+ if (fcf_in_data[FCF_FOPT] != fcf_buffer[FCF_FOPT]) {
+ fcf_differs = true;
+ LOG_INFO("FOPT requested in the programmed file differs from current setting, set 'kinetis fopt 0x%02"
+ PRIx8 "'.", fcf_in_data[FCF_FOPT]);
+ }
+
+ /* If the device has ECC flash, then we cannot re-program FCF */
+ if (fcf_differs) {
+ if (k_chip->flash_support & FS_ECC) {
+ fcf_in_data_valid = false;
+ LOG_INFO("Cannot re-program FCF. Expect verify errors at FCF (0x400-0x40f).");
+ } else {
+ LOG_INFO("Trying to re-program FCF.");
+ if (!(k_chip->flash_support & FS_PROGRAM_LONGWORD))
+ LOG_INFO("Flash re-programming may fail on this device!");
+ }
+ }
+ }
+ }
+
+ if (set_fcf && !fcf_in_data_valid) {
+ if (offset < FCF_ADDRESS) {
+ /* write part preceding FCF */
+ result = kinetis_write_inner(bank, buffer, offset, FCF_ADDRESS - offset);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ result = target_read_memory(bank->target, bank->base + FCF_ADDRESS, 4, FCF_SIZE / 4, fcf_current);
+ if (result == ERROR_OK && memcmp(fcf_current, fcf_buffer, FCF_SIZE) == 0)
+ set_fcf = false;
+
+ if (set_fcf) {
+ /* write FCF if differs from flash - eliminate multiple writes */
+ result = kinetis_write_inner(bank, fcf_buffer, FCF_ADDRESS, FCF_SIZE);
+ if (result != ERROR_OK)
+ return result;
+ }
+
+ LOG_WARNING("Flash Configuration Field written.");
+ LOG_WARNING("Reset or power off the device to make settings effective.");
+
+ if (offset + count > FCF_ADDRESS + FCF_SIZE) {
+ uint32_t delta = FCF_ADDRESS + FCF_SIZE - offset;
+ /* write part after FCF */
+ result = kinetis_write_inner(bank, buffer + delta, FCF_ADDRESS + FCF_SIZE, count - delta);
+ }
+ return result;
+
+ } else {
+ /* no FCF fiddling, normal write */
+ return kinetis_write_inner(bank, buffer, offset, count);
+ }
+}
+
+
+static int kinetis_probe_chip(struct kinetis_chip *k_chip)
+{
+ int result;
+ uint8_t fcfg1_nvmsize, fcfg1_pfsize, fcfg1_eesize, fcfg1_depart;
+ uint8_t fcfg2_pflsh;
+ uint32_t ee_size = 0;
+ uint32_t pflash_size_k, nvm_size_k, dflash_size_k;
+ uint32_t pflash_size_m;
+ unsigned num_blocks = 0;
+ unsigned maxaddr_shift = 13;
+ struct target *target = k_chip->target;
+
+ unsigned familyid = 0, subfamid = 0;
+ unsigned cpu_mhz = 120;
+ bool use_nvm_marking = false;
+ char flash_marking[12], nvm_marking[2];
+ char name[40];
+
+ k_chip->probed = false;
+ k_chip->pflash_sector_size = 0;
+ k_chip->pflash_base = 0;
+ k_chip->nvm_base = 0x10000000;
+ k_chip->progr_accel_ram = FLEXRAM;
+
+ name[0] = '\0';
+
+ if (k_chip->sim_base)
+ result = target_read_u32(target, k_chip->sim_base + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ else {
+ result = target_read_u32(target, SIM_BASE + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ if (result == ERROR_OK)
+ k_chip->sim_base = SIM_BASE;
+ else {
+ result = target_read_u32(target, SIM_BASE_KL28 + SIM_SDID_OFFSET, &k_chip->sim_sdid);
+ if (result == ERROR_OK)
+ k_chip->sim_base = SIM_BASE_KL28;
+ }
+ }