+ armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
+
+ /* This algorithm comes from DDI0487A.g, chapter J9.1 */
+
+ /* Set Normal access mode */
+ dscr = (dscr & ~DSCR_MA);
+ retval += mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+
+ if (arm->core_state == ARM_STATE_AARCH64) {
+ /* Write X0 with value 'address' using write procedure */
+ /* Step 1.a+b - Write the address for read access into DBGDTR_EL0 */
+ retval += aarch64_write_dcc_64(armv8, address & ~0x3ULL);
+ /* Step 1.c - Copy value from DTR to R0 using instruction mrs DBGDTR_EL0, x0 */
+ retval += aarch64_exec_opcode(target, ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+ /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
+ retval += aarch64_exec_opcode(target, ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), &dscr);
+ /* Step 1.e - Change DCC to memory mode */
+ dscr = dscr | DSCR_MA;
+ retval += mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+ /* Step 1.f - read DBGDTRTX and discard the value */
+ retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+ } else {
+ /* Write R0 with value 'address' using write procedure */
+ /* Step 1.a+b - Write the address for read access into DBGDTRRXint */
+ retval += aarch64_write_dcc(armv8, address & ~0x3ULL);
+ /* Step 1.c - Copy value from DTR to R0 using instruction mrc DBGDTRTXint, r0 */
+ retval += aarch64_exec_opcode(target,
+ T32_FMTITR(ARMV4_5_MRC(14, 0, 0, 0, 5, 0)), &dscr);
+ /* Step 1.d - Dummy operation to ensure EDSCR.Txfull == 1 */
+ retval += aarch64_exec_opcode(target,
+ T32_FMTITR(ARMV4_5_MCR(14, 0, 0, 0, 5, 0)), &dscr);
+ /* Step 1.e - Change DCC to memory mode */
+ dscr = dscr | DSCR_MA;
+ retval += mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+ /* Step 1.f - read DBGDTRTX and discard the value */
+ retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DTRTX, &value);
+
+ }