+
+int arm11_register_commands(struct command_context_s *cmd_ctx)
+{
+ FNC_INFO;
+
+ command_t *top_cmd, *mw_cmd;
+
+ top_cmd = register_command(cmd_ctx, NULL, "arm11",
+ NULL, COMMAND_ANY, NULL);
+
+ register_command(cmd_ctx, top_cmd, "etmr",
+ arm11_handle_etmr, COMMAND_ANY,
+ "Read Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address>");
+
+ register_command(cmd_ctx, top_cmd, "etmw",
+ arm11_handle_etmw, COMMAND_ANY,
+ "Write Embedded Trace Macrocell (ETM) register. etmr <jtag_target> <ETM register address> <value>");
+
+ /* "hardware_step" is only here to check if the default
+ * simulate + breakpoint implementation is broken.
+ * TEMPORARY! NOT DOCUMENTED!
+ */
+ register_command(cmd_ctx, top_cmd, "hardware_step",
+ arm11_handle_bool_hardware_step, COMMAND_ANY,
+ "DEBUG ONLY - Hardware single stepping"
+ " (default: disabled)");
+
+ mw_cmd = register_command(cmd_ctx, top_cmd, "memwrite",
+ NULL, COMMAND_ANY, NULL);
+ register_command(cmd_ctx, mw_cmd, "burst",
+ arm11_handle_bool_memwrite_burst, COMMAND_ANY,
+ "Enable/Disable non-standard but fast burst mode"
+ " (default: enabled)");
+ register_command(cmd_ctx, mw_cmd, "error_fatal",
+ arm11_handle_bool_memwrite_error_fatal, COMMAND_ANY,
+ "Terminate program if transfer error was found"
+ " (default: enabled)");
+
+ register_command(cmd_ctx, top_cmd, "step_irq_enable",
+ arm11_handle_bool_step_irq_enable, COMMAND_ANY,
+ "Enable interrupts while stepping"
+ " (default: disabled)");
+ register_command(cmd_ctx, top_cmd, "vcr",
+ arm11_handle_vcr, COMMAND_ANY,
+ "Control (Interrupt) Vector Catch Register");