+
+static int arm920t_mcr(struct target *target, int cpnum, uint32_t op1, uint32_t op2, uint32_t CRn, uint32_t CRm, uint32_t value)
+{
+ if (cpnum!=15)
+ {
+ LOG_ERROR("Only cp15 is supported");
+ return ERROR_FAIL;
+ }
+
+ return arm920t_write_cp15_interpreted(target, mrc_opcode(cpnum, op1, op2, CRn, CRm), 0, value);
+}
+
+/** Registers commands to access coprocessor, cache, and MMU resources. */
+int arm920t_register_commands(struct command_context *cmd_ctx)
+{
+ int retval;
+ struct command *arm920t_cmd;
+
+ retval = arm9tdmi_register_commands(cmd_ctx);
+
+ arm920t_cmd = register_command(cmd_ctx, NULL, "arm920t",
+ NULL, COMMAND_ANY,
+ "arm920t specific commands");
+
+ register_command(cmd_ctx, arm920t_cmd, "cp15",
+ arm920t_handle_cp15_command, COMMAND_EXEC,
+ "display/modify cp15 register <num> [value]");
+ register_command(cmd_ctx, arm920t_cmd, "cp15i",
+ arm920t_handle_cp15i_command, COMMAND_EXEC,
+ "display/modify cp15 (interpreted access) "
+ "<opcode> [value] [address]");
+ register_command(cmd_ctx, arm920t_cmd, "cache_info",
+ arm920t_handle_cache_info_command, COMMAND_EXEC,
+ "display information about target caches");
+ register_command(cmd_ctx, arm920t_cmd, "read_cache",
+ arm920t_handle_read_cache_command, COMMAND_EXEC,
+ "display I/D cache content");
+ register_command(cmd_ctx, arm920t_cmd, "read_mmu",
+ arm920t_handle_read_mmu_command, COMMAND_EXEC,
+ "display I/D mmu content");
+
+ return retval;
+}
+
+/** Holds methods for ARM920 targets. */
+struct target_type arm920t_target =
+{
+ .name = "arm920t",
+
+ .poll = arm7_9_poll,
+ .arch_state = arm920t_arch_state,
+
+ .target_request_data = arm7_9_target_request_data,
+
+ .halt = arm7_9_halt,
+ .resume = arm7_9_resume,
+ .step = arm7_9_step,
+
+ .assert_reset = arm7_9_assert_reset,
+ .deassert_reset = arm7_9_deassert_reset,
+ .soft_reset_halt = arm920t_soft_reset_halt,
+
+ .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+
+ .read_memory = arm920t_read_memory,
+ .write_memory = arm920t_write_memory,
+ .read_phys_memory = arm920t_read_phys_memory,
+ .write_phys_memory = arm920t_write_phys_memory,
+ .mmu = arm920_mmu,
+ .virt2phys = arm920_virt2phys,
+
+ .bulk_write_memory = arm7_9_bulk_write_memory,
+
+ .checksum_memory = arm_checksum_memory,
+ .blank_check_memory = arm_blank_check_memory,
+
+ .run_algorithm = armv4_5_run_algorithm,
+
+ .add_breakpoint = arm7_9_add_breakpoint,
+ .remove_breakpoint = arm7_9_remove_breakpoint,
+ .add_watchpoint = arm7_9_add_watchpoint,
+ .remove_watchpoint = arm7_9_remove_watchpoint,
+
+ .register_commands = arm920t_register_commands,
+ .target_create = arm920t_target_create,
+ .init_target = arm9tdmi_init_target,
+ .examine = arm7_9_examine,
+ .mrc = arm920t_mrc,
+ .mcr = arm920t_mcr,
+};