+ if (cb & 0x1)
+ {
+ LOG_DEBUG("D-Cache buffered, "
+ "drain write buffer");
+ /*
+ * Buffered ?
+ * Drain write buffer - MCR p15,0,Rd,c7,c10,4
+ */
+
+ retval = arm920t_write_cp15_interpreted(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 10, 4),
+ 0x0, 0);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ if (cb == 0x3)
+ {
+ /*
+ * Write back memory ? -> clean cache
+ *
+ * There is no way to clean cache lines using
+ * cp15 scan chain, so copy the full cache
+ * line from cache to physical memory.
+ */
+ uint8_t data[32];
+
+ LOG_DEBUG("D-Cache in 'write back' mode, "
+ "flush cache line");
+
+ retval = target_read_memory(target,
+ address & cache_mask, 1,
+ sizeof(data), &data[0]);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = armv4_5_mmu_write_physical(target,
+ &arm920t->armv4_5_mmu,
+ pa & cache_mask, 1,
+ sizeof(data), &data[0]);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ /* Cached ? */
+ if (cb & 0x2)
+ {
+ /*
+ * Cached ? -> Invalidate data cache using MVA
+ *
+ * MCR p15,0,Rd,c7,c6,1
+ */
+ LOG_DEBUG("D-Cache enabled, "
+ "invalidate cache line");
+
+ retval = arm920t_write_cp15_interpreted(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 6, 1), 0x0,
+ address & cache_mask);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+ }
+
+ /* write directly to physical memory,
+ * bypassing any read only MMU bits, etc.
+ */
+ retval = armv4_5_mmu_write_physical(target,
+ &arm920t->armv4_5_mmu, pa, size,
+ count, buffer);
+ if (retval != ERROR_OK)
+ return retval;
+ } else
+ {
+ if ((retval = arm7_9_write_memory(target, address,
+ size, count, buffer)) != ERROR_OK)
+ return retval;
+ }
+
+ /* If ICache is enabled, we have to invalidate affected ICache lines
+ * the DCache is forced to write-through,
+ * so we don't have to clean it here
+ */
+ if (arm920t->armv4_5_mmu.armv4_5_cache.i_cache_enabled)
+ {
+ if (count <= 1)
+ {
+ /* invalidate ICache single entry with MVA
+ * mcr 15, 0, r0, cr7, cr5, {1}
+ */
+ LOG_DEBUG("I-Cache enabled, "
+ "invalidating affected I-Cache line");
+ retval = arm920t_write_cp15_interpreted(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
+ 0x0, address & cache_mask);