-/* AP selection applies to future AP transactions */
-void dap_ap_select(struct swjdp_common *dap,uint8_t apsel);
-
-/* AP transactions ... synchronous given TRANS_MODE_ATOMIC */
-int dap_setup_accessport(struct swjdp_common *swjdp,
- uint32_t csw, uint32_t tar);
-int dap_ap_write_reg_u32(struct swjdp_common *swjdp,
- uint32_t addr, uint32_t value);
-int dap_ap_read_reg_u32(struct swjdp_common *swjdp,
- uint32_t addr, uint32_t *value);
-
-/* Queued JTAG ops must be completed with jtagdp_transaction_endcheck() */
-int jtagdp_transaction_endcheck(struct swjdp_common *swjdp);
-
-/* Queued MEM-AP memory mapped single word transfers */
-int mem_ap_read_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t *value);
-int mem_ap_write_u32(struct swjdp_common *swjdp, uint32_t address, uint32_t value);
-
-/* Synchronous MEM-AP memory mapped single word transfers */
-int mem_ap_read_atomic_u32(struct swjdp_common *swjdp,
- uint32_t address, uint32_t *value);
-int mem_ap_write_atomic_u32(struct swjdp_common *swjdp,
- uint32_t address, uint32_t value);
-
-/* MEM-AP memory mapped bus block transfers */
-int mem_ap_read_buf_u8(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u16(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_read_buf_u32(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-
-int mem_ap_write_buf_u8(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u16(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
-int mem_ap_write_buf_u32(struct swjdp_common *swjdp,
- uint8_t *buffer, int count, uint32_t address);
+/**
+ * Check if DAP is ADIv6
+ *
+ * @param dap The DAP to test
+ *
+ * @return true for ADIv6, false for either ADIv5 or unknown version
+ */
+static inline bool is_adiv6(const struct adiv5_dap *dap)
+{
+ return dap->adi_version == 6;
+}
+
+/**
+ * Send an adi-v5 sequence to the DAP.
+ *
+ * @param dap The DAP used for reading.
+ * @param seq The sequence to send.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_send_sequence(struct adiv5_dap *dap,
+ enum swd_special_seq seq)
+{
+ assert(dap->ops);
+ return dap->ops->send_sequence(dap, seq);
+}
+
+/**
+ * Queue a DP register read.
+ * Note that not all DP registers are readable; also, that JTAG and SWD
+ * have slight differences in DP register support.
+ *
+ * @param dap The DAP used for reading.
+ * @param reg The two-bit number of the DP register being read.
+ * @param data Pointer saying where to store the register's value
+ * (in host endianness).
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_dp_read(struct adiv5_dap *dap,
+ unsigned reg, uint32_t *data)
+{
+ assert(dap->ops);
+ return dap->ops->queue_dp_read(dap, reg, data);
+}
+
+/**
+ * Queue a DP register write.
+ * Note that not all DP registers are writable; also, that JTAG and SWD
+ * have slight differences in DP register support.
+ *
+ * @param dap The DAP used for writing.
+ * @param reg The two-bit number of the DP register being written.
+ * @param data Value being written (host endianness)
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_dp_write(struct adiv5_dap *dap,
+ unsigned reg, uint32_t data)
+{
+ assert(dap->ops);
+ return dap->ops->queue_dp_write(dap, reg, data);
+}
+
+/**
+ * Queue an AP register read.
+ *
+ * @param ap The AP used for reading.
+ * @param reg The number of the AP register being read.
+ * @param data Pointer saying where to store the register's value
+ * (in host endianness).
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_ap_read(struct adiv5_ap *ap,
+ unsigned reg, uint32_t *data)
+{
+ assert(ap->dap->ops);
+ if (ap->refcount == 0) {
+ ap->refcount = 1;
+ LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
+ }
+ return ap->dap->ops->queue_ap_read(ap, reg, data);
+}
+
+/**
+ * Queue an AP register write.
+ *
+ * @param ap The AP used for writing.
+ * @param reg The number of the AP register being written.
+ * @param data Value being written (host endianness)
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_ap_write(struct adiv5_ap *ap,
+ unsigned reg, uint32_t data)
+{
+ assert(ap->dap->ops);
+ if (ap->refcount == 0) {
+ ap->refcount = 1;
+ LOG_ERROR("BUG: refcount AP#0x%" PRIx64 " used without get", ap->ap_num);
+ }
+ return ap->dap->ops->queue_ap_write(ap, reg, data);
+}
+
+/**
+ * Queue an AP abort operation. The current AP transaction is aborted,
+ * including any update of the transaction counter. The AP is left in
+ * an unknown state (so it must be re-initialized). For use only after
+ * the AP has reported WAIT status for an extended period.
+ *
+ * @param dap The DAP used for writing.
+ * @param ack Pointer to where transaction status will be stored.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
+{
+ assert(dap->ops);
+ return dap->ops->queue_ap_abort(dap, ack);
+}
+
+/**
+ * Perform all queued DAP operations, and clear any errors posted in the
+ * CTRL_STAT register when they are done. Note that if more than one AP
+ * operation will be queued, one of the first operations in the queue
+ * should probably enable CORUNDETECT in the CTRL/STAT register.
+ *
+ * @param dap The DAP used.
+ *
+ * @return ERROR_OK for success, else a fault code.
+ */
+static inline int dap_run(struct adiv5_dap *dap)
+{
+ assert(dap->ops);
+ return dap->ops->run(dap);
+}
+
+static inline int dap_sync(struct adiv5_dap *dap)
+{
+ assert(dap->ops);
+ if (dap->ops->sync)
+ return dap->ops->sync(dap);
+ return ERROR_OK;
+}
+
+static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
+ uint32_t *value)
+{
+ int retval;
+
+ retval = dap_queue_dp_read(dap, reg, value);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return dap_run(dap);
+}
+
+static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
+ uint32_t mask, uint32_t value, int timeout)
+{
+ assert(timeout > 0);
+ assert((value & mask) == value);
+
+ int ret;
+ uint32_t regval;
+ LOG_DEBUG("DAP: poll %x, mask 0x%08" PRIx32 ", value 0x%08" PRIx32,
+ reg, mask, value);
+ do {
+ ret = dap_dp_read_atomic(dap, reg, ®val);
+ if (ret != ERROR_OK)
+ return ret;
+
+ if ((regval & mask) == value)
+ break;
+
+ alive_sleep(10);
+ } while (--timeout);
+
+ if (!timeout) {
+ LOG_DEBUG("DAP: poll %x timeout", reg);
+ return ERROR_WAIT;
+ } else {
+ return ERROR_OK;
+ }
+}
+
+/* Queued MEM-AP memory mapped single word transfers. */
+int mem_ap_read_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t *value);
+int mem_ap_write_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t value);
+
+/* Synchronous MEM-AP memory mapped single word transfers. */
+int mem_ap_read_atomic_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t *value);
+int mem_ap_write_atomic_u32(struct adiv5_ap *ap,
+ target_addr_t address, uint32_t value);
+
+/* Synchronous MEM-AP memory mapped bus block transfers. */
+int mem_ap_read_buf(struct adiv5_ap *ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+int mem_ap_write_buf(struct adiv5_ap *ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+
+/* Synchronous, non-incrementing buffer functions for accessing fifos. */
+int mem_ap_read_buf_noincr(struct adiv5_ap *ap,
+ uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);
+int mem_ap_write_buf_noincr(struct adiv5_ap *ap,
+ const uint8_t *buffer, uint32_t size, uint32_t count, target_addr_t address);