+ /* true if tar_value is in sync with TAR register */
+ bool tar_valid;
+};
+
+
+/**
+ * This represents an ARM Debug Interface (v5) Debug Access Port (DAP).
+ * A DAP has two types of component: one Debug Port (DP), which is a
+ * transport agent; and at least one Access Port (AP), controlling
+ * resource access.
+ *
+ * There are two basic DP transports: JTAG, and ARM's low pin-count SWD.
+ * Accordingly, this interface is responsible for hiding the transport
+ * differences so upper layer code can largely ignore them.
+ *
+ * When the chip is implemented with JTAG-DP or SW-DP, the transport is
+ * fixed as JTAG or SWD, respectively. Chips incorporating SWJ-DP permit
+ * a choice made at board design time (by only using the SWD pins), or
+ * as part of setting up a debug session (if all the dual-role JTAG/SWD
+ * signals are available).
+ */
+struct adiv5_dap {
+ const struct dap_ops *ops;
+
+ /* dap transaction list for WAIT support */
+ struct list_head cmd_journal;
+
+ struct jtag_tap *tap;
+ /* Control config */
+ uint32_t dp_ctrl_stat;
+
+ struct adiv5_ap ap[256];
+
+ /* The current manually selected AP by the "dap apsel" command */
+ uint32_t apsel;
+
+ /**
+ * Cache for DP_SELECT register. A value of DP_SELECT_INVALID
+ * indicates no cached value and forces rewrite of the register.
+ */
+ uint32_t select;
+
+ /* information about current pending SWjDP-AHBAP transaction */
+ uint8_t ack;
+
+ /**
+ * Holds the pointer to the destination word for the last queued read,
+ * for use with posted AP read sequence optimization.
+ */
+ uint32_t *last_read;
+