+static const struct command_registration arm_exec_command_handlers[] = {
+ {
+ .name = "reg",
+ .handler = handle_armv4_5_reg_command,
+ .mode = COMMAND_EXEC,
+ .help = "display ARM core registers",
+ .usage = "",
+ },
+ {
+ .name = "core_state",
+ .handler = handle_armv4_5_core_state_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['arm'|'thumb']",
+ .help = "display/change ARM core state",
+ },
+ {
+ .name = "disassemble",
+ .handler = handle_arm_disassemble_command,
+ .mode = COMMAND_EXEC,
+ .usage = "address [count ['thumb']]",
+ .help = "disassemble instructions ",
+ },
+ {
+ .name = "mcr",
+ .mode = COMMAND_EXEC,
+ .jim_handler = &jim_mcrmrc,
+ .help = "write coprocessor register",
+ .usage = "cpnum op1 CRn CRm op2 value",
+ },
+ {
+ .name = "mrc",
+ .jim_handler = &jim_mcrmrc,
+ .help = "read coprocessor register",
+ .usage = "cpnum op1 CRn CRm op2",
+ },
+ {
+ "semihosting",
+ .handler = handle_arm_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting operations",
+ },
+ {
+ "semihosting_cmdline",
+ .handler = handle_arm_semihosting_cmdline,
+ .mode = COMMAND_EXEC,
+ .usage = "arguments",
+ .help = "command line arguments to be passed to program",
+ },
+ {
+ "semihosting_fileio",
+ .handler = handle_arm_semihosting_fileio_command,
+ .mode = COMMAND_EXEC,
+ .usage = "['enable'|'disable']",
+ .help = "activate support for semihosting fileio operations",
+ },
+
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm_command_handlers[] = {
+ {
+ .name = "arm",
+ .mode = COMMAND_ANY,
+ .help = "ARM command group",
+ .usage = "",
+ .chain = arm_exec_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};
+
+int arm_get_gdb_reg_list(struct target *target,
+ struct reg **reg_list[], int *reg_list_size,
+ enum target_register_class reg_class)
+{
+ struct arm *arm = target_to_arm(target);
+ unsigned int i;
+
+ if (!is_arm_mode(arm->core_mode)) {
+ LOG_ERROR("not a valid arm core mode - communication failure?");
+ return ERROR_FAIL;
+ }
+
+ switch (reg_class) {
+ case REG_CLASS_GENERAL:
+ *reg_list_size = 26;
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+ for (i = 0; i < 16; i++)
+ (*reg_list)[i] = arm_reg_current(arm, i);
+
+ /* For GDB compatibility, take FPA registers size into account and zero-fill it*/
+ for (i = 16; i < 24; i++)
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
+
+ (*reg_list)[25] = arm->cpsr;
+
+ return ERROR_OK;
+ break;
+
+ case REG_CLASS_ALL:
+ *reg_list_size = (arm->core_type != ARM_MODE_MON ? 48 : 51);
+ *reg_list = malloc(sizeof(struct reg *) * (*reg_list_size));
+
+ for (i = 0; i < 16; i++)
+ (*reg_list)[i] = arm_reg_current(arm, i);
+
+ for (i = 13; i < ARRAY_SIZE(arm_core_regs); i++) {
+ int reg_index = arm->core_cache->reg_list[i].number;
+ if (!(arm_core_regs[i].mode == ARM_MODE_MON
+ && arm->core_type != ARM_MODE_MON))
+ (*reg_list)[reg_index] = &(arm->core_cache->reg_list[i]);
+ }
+
+ /* When we supply the target description, there is no need for fake FPA */
+ for (i = 16; i < 24; i++) {
+ (*reg_list)[i] = &arm_gdb_dummy_fp_reg;
+ (*reg_list)[i]->size = 0;
+ }
+ (*reg_list)[24] = &arm_gdb_dummy_fps_reg;
+ (*reg_list)[24]->size = 0;
+
+ return ERROR_OK;
+ break;
+
+ default:
+ LOG_ERROR("not a valid register class type in query.");
+ return ERROR_FAIL;
+ break;
+ }
+}
+