+/*
+ * Cortex-A8 implementation of Debug Programmer's Model
+ *
+ * NOTE the invariant: these routines return with DSCR_INSTR_COMP set,
+ * so there's no need to poll for it before executing an instruction.
+ *
+ * NOTE that in several of these cases the "stall" mode might be useful.
+ * It'd let us queue a few operations together... prepare/finish might
+ * be the places to enable/disable that mode.
+ */
+
+static inline struct cortex_a8_common *dpm_to_a8(struct arm_dpm *dpm)
+{
+ return container_of(dpm, struct cortex_a8_common, armv7a_common.dpm);
+}
+
+static int cortex_a8_write_dcc(struct cortex_a8_common *a8, uint32_t data)
+{
+ LOG_DEBUG("write DCC 0x%08" PRIx32, data);
+ return mem_ap_write_u32(&a8->armv7a_common.dap,
+ a8->armv7a_common.debug_base + CPUDBG_DTRRX, data);
+}
+
+static int cortex_a8_read_dcc(struct cortex_a8_common *a8, uint32_t *data,
+ uint32_t *dscr_p)
+{
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ if (dscr_p)
+ dscr = *dscr_p;
+
+ /* Wait for DTRRXfull */
+ long long then = timeval_ms();
+ while ((dscr & DSCR_DTR_TX_FULL) == 0) {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for read dcc");
+ return ERROR_FAIL;
+ }
+ }
+
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DTRTX, data);
+ if (retval != ERROR_OK)
+ return retval;
+ //LOG_DEBUG("read DCC 0x%08" PRIx32, *data);
+
+ if (dscr_p)
+ *dscr_p = dscr;
+
+ return retval;
+}
+
+static int cortex_a8_dpm_prepare(struct arm_dpm *dpm)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ struct adiv5_dap *swjdp = &a8->armv7a_common.dap;
+ uint32_t dscr;
+ int retval;
+
+ /* set up invariant: INSTR_COMP is set after ever DPM operation */
+ long long then = timeval_ms();
+ for (;;)
+ {
+ retval = mem_ap_read_atomic_u32(swjdp,
+ a8->armv7a_common.debug_base + CPUDBG_DSCR,
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ if ((dscr & DSCR_INSTR_COMP) != 0)
+ break;
+ if (timeval_ms() > then + 1000)
+ {
+ LOG_ERROR("Timeout waiting for dpm prepare");
+ return ERROR_FAIL;
+ }
+ }
+
+ /* this "should never happen" ... */
+ if (dscr & DSCR_DTR_RX_FULL) {
+ LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
+ /* Clear DCCRX */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+ }
+
+ return retval;
+}
+
+static int cortex_a8_dpm_finish(struct arm_dpm *dpm)
+{
+ /* REVISIT what could be done here? */
+ return ERROR_OK;
+}
+
+static int cortex_a8_instr_write_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+}
+
+static int cortex_a8_instr_write_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ retval = cortex_a8_write_dcc(a8, data);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* DCCRX to R0, "MCR p14, 0, R0, c0, c5, 0", 0xEE000E15 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MRC(14, 0, 0, 0, 5, 0),
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* then the opcode, taking data from R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+
+ return retval;
+}
+
+static int cortex_a8_instr_cpsr_sync(struct arm_dpm *dpm)
+{
+ struct target *target = dpm->arm->target;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ /* "Prefetch flush" after modifying execution status in CPSR */
+ return cortex_a8_exec_opcode(target,
+ ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+ &dscr);
+}
+
+static int cortex_a8_instr_read_data_dcc(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ int retval;
+ uint32_t dscr = DSCR_INSTR_COMP;
+
+ /* the opcode, writing data to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+
+static int cortex_a8_instr_read_data_r0(struct arm_dpm *dpm,
+ uint32_t opcode, uint32_t *data)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t dscr = DSCR_INSTR_COMP;
+ int retval;
+
+ /* the opcode, writing data to R0 */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ opcode,
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* write R0 to DCC */
+ retval = cortex_a8_exec_opcode(
+ a8->armv7a_common.armv4_5_common.target,
+ ARMV4_5_MCR(14, 0, 0, 0, 5, 0),
+ &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ return cortex_a8_read_dcc(a8, data, &dscr);
+}
+
+static int cortex_a8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
+ uint32_t addr, uint32_t control)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t vr = a8->armv7a_common.debug_base;
+ uint32_t cr = a8->armv7a_common.debug_base;
+ int retval;
+
+ switch (index_t) {
+ case 0 ... 15: /* breakpoints */
+ vr += CPUDBG_BVR_BASE;
+ cr += CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31: /* watchpoints */
+ vr += CPUDBG_WVR_BASE;
+ cr += CPUDBG_WCR_BASE;
+ index_t -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ vr += 4 * index_t;
+ cr += 4 * index_t;
+
+ LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
+ (unsigned) vr, (unsigned) cr);
+
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ vr, addr);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = cortex_a8_dap_write_memap_register_u32(dpm->arm->target,
+ cr, control);
+ return retval;
+}
+
+static int cortex_a8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
+{
+ struct cortex_a8_common *a8 = dpm_to_a8(dpm);
+ uint32_t cr;
+
+ switch (index_t) {
+ case 0 ... 15:
+ cr = a8->armv7a_common.debug_base + CPUDBG_BCR_BASE;
+ break;
+ case 16 ... 31:
+ cr = a8->armv7a_common.debug_base + CPUDBG_WCR_BASE;
+ index_t -= 16;
+ break;
+ default:
+ return ERROR_FAIL;
+ }
+ cr += 4 * index_t;
+
+ LOG_DEBUG("A8: bpwp disable, cr %08x", (unsigned) cr);
+
+ /* clear control register */
+ return cortex_a8_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
+}
+
+static int cortex_a8_dpm_setup(struct cortex_a8_common *a8, uint32_t didr)
+{
+ struct arm_dpm *dpm = &a8->armv7a_common.dpm;
+ int retval;
+
+ dpm->arm = &a8->armv7a_common.armv4_5_common;
+ dpm->didr = didr;
+
+ dpm->prepare = cortex_a8_dpm_prepare;
+ dpm->finish = cortex_a8_dpm_finish;
+
+ dpm->instr_write_data_dcc = cortex_a8_instr_write_data_dcc;
+ dpm->instr_write_data_r0 = cortex_a8_instr_write_data_r0;
+ dpm->instr_cpsr_sync = cortex_a8_instr_cpsr_sync;
+
+ dpm->instr_read_data_dcc = cortex_a8_instr_read_data_dcc;
+ dpm->instr_read_data_r0 = cortex_a8_instr_read_data_r0;
+
+ dpm->bpwp_enable = cortex_a8_bpwp_enable;
+ dpm->bpwp_disable = cortex_a8_bpwp_disable;
+
+ retval = arm_dpm_setup(dpm);
+ if (retval == ERROR_OK)
+ retval = arm_dpm_initialize(dpm);
+
+ return retval;
+}
+
+