+ LOG_ERROR("jtag device number '%s' not defined", args[1]);
+ exit(-1);
+ }
+
+ if (arm7_9->etm_ctx)
+ {
+ etb_t *etb = malloc(sizeof(etb_t));
+
+ arm7_9->etm_ctx->capture_driver_priv = etb;
+
+ etb->chain_pos = strtoul(args[1], NULL, 0);
+ etb->cur_scan_chain = -1;
+ etb->reg_cache = NULL;
+ etb->ram_width = 0;
+ etb->ram_depth = 0;
+ }
+ else
+ {
+ LOG_ERROR("target has no ETM defined, ETB left unconfigured");
+ }
+
+ return ERROR_OK;
+}
+
+int etb_init(etm_context_t *etm_ctx)
+{
+ etb_t *etb = etm_ctx->capture_driver_priv;
+
+ etb->etm_ctx = etm_ctx;
+
+ /* identify ETB RAM depth and width */
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_DEPTH]);
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WIDTH]);
+ jtag_execute_queue();
+
+ etb->ram_depth = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_DEPTH].value, 0, 32);
+ etb->ram_width = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WIDTH].value, 0, 32);
+
+ return ERROR_OK;
+}
+
+trace_status_t etb_status(etm_context_t *etm_ctx)
+{
+ etb_t *etb = etm_ctx->capture_driver_priv;
+
+ etb->etm_ctx = etm_ctx;
+
+ /* if tracing is currently idle, return this information */
+ if (etm_ctx->capture_status == TRACE_IDLE)
+ {
+ return etm_ctx->capture_status;
+ }
+ else if (etm_ctx->capture_status & TRACE_RUNNING)
+ {
+ reg_t *etb_status_reg = &etb->reg_cache->reg_list[ETB_STATUS];
+ int etb_timeout = 100;
+
+ /* trace is running, check the ETB status flags */
+ etb_get_reg(etb_status_reg);
+
+ /* check Full bit to identify an overflow */
+ if (buf_get_u32(etb_status_reg->value, 0, 1) == 1)
+ etm_ctx->capture_status |= TRACE_OVERFLOWED;
+
+ /* check Triggered bit to identify trigger condition */
+ if (buf_get_u32(etb_status_reg->value, 1, 1) == 1)
+ etm_ctx->capture_status |= TRACE_TRIGGERED;
+
+ /* check AcqComp to identify trace completion */
+ if (buf_get_u32(etb_status_reg->value, 2, 1) == 1)
+ {
+ while (etb_timeout-- && (buf_get_u32(etb_status_reg->value, 3, 1) == 0))
+ {
+ /* wait for data formatter idle */
+ etb_get_reg(etb_status_reg);
+ }
+
+ if (etb_timeout == 0)
+ {
+ LOG_ERROR("AcqComp set but DFEmpty won't go high, ETB status: 0x%x",
+ buf_get_u32(etb_status_reg->value, 0, etb_status_reg->size));
+ }
+
+ if (!(etm_ctx->capture_status && TRACE_TRIGGERED))
+ {
+ LOG_ERROR("trace completed, but no trigger condition detected");
+ }
+
+ etm_ctx->capture_status &= ~TRACE_RUNNING;
+ etm_ctx->capture_status |= TRACE_COMPLETED;
+ }
+ }
+
+ return etm_ctx->capture_status;
+}
+
+int etb_read_trace(etm_context_t *etm_ctx)
+{
+ etb_t *etb = etm_ctx->capture_driver_priv;
+ int first_frame = 0;
+ int num_frames = etb->ram_depth;
+ u32 *trace_data = NULL;
+ int i, j;
+
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_STATUS]);
+ etb_read_reg(&etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER]);
+ jtag_execute_queue();
+
+ /* check if we overflowed, and adjust first frame of the trace accordingly
+ * if we didn't overflow, read only up to the frame that would be written next,
+ * i.e. don't read invalid entries
+ */
+ if (buf_get_u32(etb->reg_cache->reg_list[ETB_STATUS].value, 0, 1))
+ {
+ first_frame = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);
+ }
+ else
+ {
+ num_frames = buf_get_u32(etb->reg_cache->reg_list[ETB_RAM_WRITE_POINTER].value, 0, 32);