field.in_value = NULL;
jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
field.in_value = NULL;
jtag_set_check_value(&field, tap->expected, tap->expected_mask, NULL);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
/* DANGER!!! this must be here. It will make sure that the arguments
* to jtag_set_check_value() does not go out of scope! */
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
- fields[1].in_handler = buf_to_u32_handler;
- fields[1].in_handler_priv = (u8*)&field1[i];
+ fields[1].in_handler = buf_to_u32_handler; /* deprecated! invoke this from user code! */
+ fields[1].in_handler_priv = (u8*)&field1[i];
- noconsume_path[0] = TAP_SDS;
- noconsume_path[1] = TAP_CD;
- noconsume_path[2] = TAP_E1D;
- noconsume_path[3] = TAP_PD;
- noconsume_path[4] = TAP_E2D;
- noconsume_path[5] = TAP_SD;
+ noconsume_path[0] = TAP_DRSELECT;
+ noconsume_path[1] = TAP_DRCAPTURE;
+ noconsume_path[2] = TAP_DREXIT1;
+ noconsume_path[3] = TAP_DRPAUSE;
+ noconsume_path[4] = TAP_DREXIT2;
+ noconsume_path[5] = TAP_DRSHIFT;
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
buf_set_u32(&field0, 1, 1, xscale->hold_rst);
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
fields[2].in_value = NULL;
jtag_set_check_value(fields+2, &field2_check_value, &field2_check_mask, NULL);
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD is b010 for Main IC and b011 for Mini IC */
{
buf_set_u32(packet, 0, 32, buffer[word]);
cmd = parity(*((u32*)packet));
{
buf_set_u32(packet, 0, 32, buffer[word]);
cmd = parity(*((u32*)packet));
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.ldic); /* LDIC */
/* CMD for invalidate IC line b000, bits [6:4] b000 */
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
target->debug_reason = DBG_REASON_SINGLESTEP;
/* calculate PC of next instruction */
if ((retval = arm_simulate_step(target, &next_pc)) != ERROR_OK)
{
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
target_read_u32(target, current_pc, ¤t_opcode);
LOG_ERROR("BUG: couldn't calculate PC of next instruction, current opcode was 0x%8.8x", current_opcode);
return retval;
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
/* select DCSR instruction (set endstate to R-T-I to ensure we don't
* end up in T-L-R, which would reset JTAG
*/
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
xscale_jtag_set_instr(xscale->jtag_info.tap, xscale->jtag_info.dcsr);
/* set Hold reset, Halt mode and Trap Reset */
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
xscale_load_ic(target, 1, 0x0, xscale->low_vectors);
xscale_load_ic(target, 1, 0xffff0000, xscale->high_vectors);
int retval;
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
int retval;
LOG_DEBUG("address: 0x%8.8x, size: 0x%8.8x, count: 0x%8.8x", address, size, count);
LOG_INFO("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
LOG_INFO("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
(((instruction.type == ARM_B) ||
(instruction.type == ARM_BL) ||
(instruction.type == ARM_BLX)) &&
(((instruction.type == ARM_B) ||
(instruction.type == ARM_BL) ||
(instruction.type == ARM_BLX)) &&
int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
int xscale_handle_mmu_command(command_context_t *cmd_ctx, char *cmd, char **args, int argc)
{
target_t *target = get_current_target(cmd_ctx);
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
command_print(cmd_ctx, "icache %s", (xscale->armv4_5_mmu.armv4_5_cache.i_cache_enabled) ? "enabled" : "disabled");
if (dcache)
- command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
+ command_print(cmd_ctx, "dcache %s", (xscale->armv4_5_mmu.armv4_5_cache.d_u_cache_enabled) ? "enabled" : "disabled");
register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
register_command(cmd_ctx, xscale_cmd, "icache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the ICache");
register_command(cmd_ctx, xscale_cmd, "dcache", xscale_handle_idcache_command, COMMAND_EXEC, "['enable'|'disable'] the DCache");
- register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_idcache_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
+ register_command(cmd_ctx, xscale_cmd, "vector_catch", xscale_handle_vector_catch_command, COMMAND_EXEC, "<mask> of vectors that should be catched");
register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");
register_command(cmd_ctx, xscale_cmd, "trace_buffer", xscale_handle_trace_buffer_command, COMMAND_EXEC, "<enable|disable> ['fill' [n]|'wrap']");