- # four registers in order: SMC_SETUP3, SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3.
-
- mww 0xffffec30 0x00020002
- mww 0xffffec34 0x04040404
- mww 0xffffec38 0x00070007
- mww 0xffffec3c 0x00030003
-
- # Identify NandFlash bank 0. Disabled at the moment because a memory driver is not yet complete.
-
-# nand probe 0
+ # a number of registers. The first step involves setting up the general I/O pins on the processor
+ # to be able to interface and support the external memory.
+
+ mww 0xfffffc10 0x00000010 ;# PMC_PCER : enable PIOC clock
+ mww 0xfffff800 0x00006000 ;# PIOC_PER : enable PIO function for 13(RDY/~BSY) and 14(~CS)
+ mww 0xfffff810 0x00004000 ;# PIOC_OER : enable output on 14
+ mww 0xfffff814 0x00002000 ;# PIOC_ODR : disable output on 13
+ mww 0xfffff830 0x00004000 ;# PIOC_SODR : set 14 to disable NAND
+
+ # The exact physical timing characteristics for the memory type used on the current board
+ # (MT29F2G08AACWP) can be established by setting four registers in order: SMC_SETUP3,
+ # SMC_PULSE3, SMC_CYCLE3, and SMC_MODE3. Computing the exact values of these registers
+ # is a little tedious to do here. If you have questions about how to do this, Atmel has
+ # a decent application note #6255B that covers this process.
+
+ mww 0xffffec30 0x00020002 ;# SMC_SETUP3 : 2 clock cycle setup for NRD and NWE
+ mww 0xffffec34 0x04040404 ;# SMC_PULSE3 : 4 clock cycle pulse for all signals
+ mww 0xffffec38 0x00070006 ;# SMC_CYCLE3 : 7 clock cycle NRD and 6 NWE cycle
+ mww 0xffffec3C 0x00020003 ;# SMC_MODE3 : NRD and NWE control, no NWAIT, 8-bit DBW,
+
+ mww 0xffffe800 0x00000001 ;# ECC_CR : reset the ECC parity registers
+ mww 0xffffe804 0x00000002 ;# ECC_MR : page size is 2112 words (word is 8 bits)
+
+ # Identify NandFlash bank 0.
+
+ nand probe nandflash_cs3
+
+ # The AT91SAM9G20-EK evaluation board has build-in serial data flash also.