-set AT91_PMC_MCKR [expr ($AT91_PMC + 0x30)] ;# Master Clock Register
-set AT91_PMC_CSS [expr (3 << 0)] ;# Master Clock Selection
-set AT91_PMC_CSS_SLOW [expr (0 << 0)]
-set AT91_PMC_CSS_MAIN [expr (1 << 0)]
-set AT91_PMC_CSS_PLLA [expr (2 << 0)]
-set AT91_PMC_CSS_PLLB [expr (3 << 0)]
-set AT91_PMC_CSS_UPLL [expr (3 << 0)] ;# [some SAM9 only]
-set AT91_PMC_PRES [expr (7 << 2)] ;# Master Clock Prescaler
-set AT91_PMC_PRES_1 [expr (0 << 2)]
-set AT91_PMC_PRES_2 [expr (1 << 2)]
-set AT91_PMC_PRES_4 [expr (2 << 2)]
-set AT91_PMC_PRES_8 [expr (3 << 2)]
-set AT91_PMC_PRES_16 [expr (4 << 2)]
-set AT91_PMC_PRES_32 [expr (5 << 2)]
-set AT91_PMC_PRES_64 [expr (6 << 2)]
-set AT91_PMC_MDIV [expr (3 << 8)] ;# Master Clock Division
-set AT91RM9200_PMC_MDIV_1 [expr (0 << 8)] ;# [AT91RM9200 only]
-set AT91RM9200_PMC_MDIV_2 [expr (1 << 8)]
-set AT91RM9200_PMC_MDIV_3 [expr (2 << 8)]
-set AT91RM9200_PMC_MDIV_4 [expr (3 << 8)]
-set AT91SAM9_PMC_MDIV_1 [expr (0 << 8)] ;# [SAM9,CAP9 only]
-set AT91SAM9_PMC_MDIV_2 [expr (1 << 8)]
-set AT91SAM9_PMC_MDIV_4 [expr (2 << 8)]
-set AT91SAM9_PMC_MDIV_6 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91SAM9_PMC_MDIV_3 [expr (3 << 8)] ;# [some SAM9 only]
-set AT91_PMC_PDIV [expr (1 << 12)] ;# Processor Clock Division [some SAM9 only]
-set AT91_PMC_PDIV_1 [expr (0 << 12)]
-set AT91_PMC_PDIV_2 [expr (1 << 12)]
-set AT91_PMC_PLLADIV2 [expr (1 << 12)] ;# PLLA divisor by 2 [some SAM9 only]
-set AT91_PMC_PLLADIV2_OFF [expr (0 << 12)]
-set AT91_PMC_PLLADIV2_ON [expr (1 << 12)]
+set AT91_CKGR_PLLAR [expr {$AT91_PMC + 0x28}] ;# PLL A Register
+set AT91_CKGR_PLLBR [expr {$AT91_PMC + 0x2c}] ;# PLL B Register
+set AT91_PMC_DIV [expr {0xff << 0}] ;# Divider
+set AT91_PMC_PLLCOUNT [expr {0x3f << 8}] ;# PLL Counter
+set AT91_PMC_OUT [expr {3 << 14}] ;# PLL Clock Frequency Range
+set AT91_PMC_MUL [expr {0x7ff << 16}] ;# PLL Multiplier
+set AT91_PMC_USBDIV [expr {3 << 28}] ;# USB Divisor (PLLB only)
+set AT91_PMC_USBDIV_1 [expr {0 << 28}]
+set AT91_PMC_USBDIV_2 [expr {1 << 28}]
+set AT91_PMC_USBDIV_4 [expr {2 << 28}]
+set AT91_PMC_USB96M [expr {1 << 28}] ;# Divider by 2 Enable (PLLB only)
+set AT91_PMC_PLLA_WR_ERRATA [expr {1 << 29}] ;# Bit 29 must always be set to 1 when programming the CKGR_PLLAR register