remove BUILD_IOUTIL symbol

[openocd.git] / doc / openocd.texi

diff --git a/doc/openocd.texi b/doc/openocd.texi
index b32ed213f16aa1f6f8000451fbcb5c0fe8464ad1..7e232117cdb10af4eba4e5975ecb7ae8ef0f0345 100644 (file)
--- a/doc/openocd.texi
+++ b/doc/openocd.texi
@@ -1524,7 +1524,7 @@ proc setc15 @{regs value@} @{
 
     echo [format "set p15 0x%04x, 0x%08x" $regs $value]
 
-    mcr 15 [expr ($regs>>12)&0x7] \
+    arm mcr 15 [expr ($regs>>12)&0x7] \
         [expr ($regs>>0)&0xf] [expr ($regs>>4)&0xf] \
         [expr ($regs>>8)&0x7] $value
 @}
@@ -3117,6 +3117,7 @@ There are several variants defined:
 @code{pxa27x} ... instruction register length is 7 bits
 @item @code{pxa250}, @code{pxa255},
 @code{pxa26x} ... instruction register length is 5 bits
+@item @code{pxa3xx} ... instruction register length is 11 bits
 @end itemize
 @end itemize
 @end deffn
@@ -5608,6 +5609,24 @@ with a handful of exceptions.
 ThumbEE disassembly currently has no explicit support.
 @end deffn
 
+@deffn Command {arm mcr} pX op1 CRn CRm op2 value
+Write @var{value} to a coprocessor @var{pX} register
+passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and using the MCR instruction.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
+@deffn Command {arm mrc} pX coproc op1 CRn CRm op2 
+Read a coprocessor @var{pX} register passing parameters @var{CRn},
+@var{CRm}, opcodes @var{opc1} and @var{opc2},
+and the MRC instruction.
+Returns the result so it can be manipulated by Jim scripts.
+(Parameter sequence matches the ARM instruction, but omits
+an ARM register.)
+@end deffn
+
 @deffn Command {arm reg}
 Display a table of all banked core registers, fetching the current value from every
 core mode if necessary.