static int imx27_command(struct nand_device *nand, uint8_t command);
static int imx27_address(struct nand_device *nand, uint8_t address);
-static int imx27_controller_ready(struct nand_device *nand, int tout);
NAND_DEVICE_COMMAND_HANDLER(imx27_nand_device_command)
{
}
nand->controller_priv = mx2_nf_info;
- mx2_nf_info->target = get_target(CMD_ARGV[1]);
- if (mx2_nf_info->target == NULL) {
- LOG_ERROR("target '%s' not defined", CMD_ARGV[1]);
- return ERROR_FAIL;
- }
if (CMD_ARGC < 3) {
LOG_ERROR("use \"nand device imx27 target noecc|hwecc\"");
return ERROR_FAIL;
mx2_nf_info->optype = MX2_NF_DATAOUT_PAGE;
mx2_nf_info->fin = MX2_NF_FIN_NONE;
mx2_nf_info->flags.target_little_endian =
- (mx2_nf_info->target->endianness == TARGET_LITTLE_ENDIAN);
+ (nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
- * testing host endianess
+ * testing host endianness
*/
x = 1;
if (*(char *) &x == 1)
static int imx27_init(struct nand_device *nand)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int validate_target_result;
uint16_t buffsize_register_content;
static int imx27_read_data(struct nand_device *nand, void *data)
{
- struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int validate_target_result;
int try_data_output_from_nand_chip;
/*
return ERROR_NAND_OPERATION_FAILED;
}
-static int imx27_nand_ready(struct nand_device *nand, int timeout)
-{
- return imx27_controller_ready(nand, timeout);
-}
-
static int imx27_reset(struct nand_device *nand)
{
/*
static int imx27_command(struct nand_device *nand, uint8_t command)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int validate_target_result;
int poll_result;
/*
static int imx27_address(struct nand_device *nand, uint8_t address)
{
- struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int validate_target_result;
int poll_result;
/*
return ERROR_OK;
}
-static int imx27_controller_ready(struct nand_device *nand, int tout)
+static int imx27_nand_ready(struct nand_device *nand, int tout)
{
uint16_t poll_complete_status;
- struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int validate_target_result;
/*
uint32_t oob_size)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int retval;
uint16_t nand_status_content;
uint16_t swap1, swap2, new_swap1;
uint32_t oob_size)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int retval;
uint16_t swap1, swap2, new_swap1;
if (data_size % 2) {
return retval;
}
/* Reset address_cycles before imx27_command ?? */
- retval = ERROR_OK;
- retval |= imx27_command(nand, NAND_CMD_READ0);
-
- retval |= imx27_address(nand, 0); //col
- retval |= imx27_address(nand, 0); //col
- retval |= imx27_address(nand, page & 0xff); //page address
- retval |= imx27_address(nand, (page >> 8) & 0xff); //page address
- retval |= imx27_address(nand, (page >> 16) & 0xff); //page address
- retval |= imx27_command(nand, NAND_CMD_READSTART);
+ retval = imx27_command(nand, NAND_CMD_READ0);
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_address(nand, 0); //col
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_address(nand, 0); //col
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_address(nand, page & 0xff); //page address
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_address(nand, (page >> 8) & 0xff); //page address
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_address(nand, (page >> 16) & 0xff); //page address
+ if (retval != ERROR_OK) return retval;
+ retval = imx27_command(nand, NAND_CMD_READSTART);
+ if (retval != ERROR_OK) return retval;
target_write_u16(target, MX2_NF_BUFADDR, 0);
mx2_nf_info->fin = MX2_NF_FIN_DATAOUT;
static int initialize_nf_controller(struct nand_device *nand)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
uint16_t work_mode;
uint16_t temp;
/*
static int validate_target_state(struct nand_device *nand)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
if (target->state != TARGET_HALTED) {
LOG_ERROR(target_not_halted_err_msg);
static int do_data_output(struct nand_device *nand)
{
struct mx2_nf_controller *mx2_nf_info = nand->controller_priv;
- struct target *target = mx2_nf_info->target;
+ struct target *target = nand->target;
int poll_result;
uint16_t ecc_status;
switch(mx2_nf_info->fin) {
.read_data = &imx27_read_data,
.write_page = &imx27_write_page,
.read_page = &imx27_read_page,
- .controller_ready = &imx27_controller_ready,
.nand_ready = &imx27_nand_ready,
};