David Brownell <david-b@pacbell.net>:

[openocd.git] / src / flash / nand.h

diff --git a/src/flash/nand.h b/src/flash/nand.h
index bd9554c344c4e8ac027189858c9a08792866d588..0ee1ffe83fd38882187a8f4c54e52b67c7c53022 100644 (file)
--- a/src/flash/nand.h
+++ b/src/flash/nand.h
@@ -95,11 +95,12 @@ enum
        NAND_MFR_RENESAS = 0x07,
        NAND_MFR_STMICRO = 0x20,
        NAND_MFR_HYNIX = 0xad,
+       NAND_MFR_MICRON = 0x2c,
 };
 
 typedef struct nand_manufacturer_s
 {
-    int id;
+       int id;
        char *name;
 } nand_manufacturer_t;
 
@@ -115,43 +116,43 @@ typedef struct nand_info_s
 
 /* Option constants for bizarre disfunctionality and real features
  */
-enum { 
+enum {
        /* Chip can not auto increment pages */
        NAND_NO_AUTOINCR = 0x00000001,
-       
+
        /* Buswitdh is 16 bit */
        NAND_BUSWIDTH_16 = 0x00000002,
-       
+
        /* Device supports partial programming without padding */
        NAND_NO_PADDING = 0x00000004,
-       
+
        /* Chip has cache program function */
        NAND_CACHEPRG = 0x00000008,
-       
+
        /* Chip has copy back function */
        NAND_COPYBACK = 0x00000010,
-       
+
        /* AND Chip which has 4 banks and a confusing page / block
         * assignment. See Renesas datasheet for further information */
        NAND_IS_AND = 0x00000020,
-       
+
        /* Chip has a array of 4 pages which can be read without
         * additional ready /busy waits */
        NAND_4PAGE_ARRAY = 0x00000040,
-       
+
        /* Chip requires that BBT is periodically rewritten to prevent
         * bits from adjacent blocks from 'leaking' in altering data.
         * This happens with the Renesas AG-AND chips, possibly others.  */
        BBT_AUTO_REFRESH = 0x00000080,
-       
+
        /* Chip does not require ready check on read. True
         * for all large page devices, as they do not support
         * autoincrement.*/
        NAND_NO_READRDY = 0x00000100,
-       
+
        /* Options valid for Samsung large page devices */
        NAND_SAMSUNG_LP_OPTIONS = (NAND_NO_PADDING | NAND_CACHEPRG | NAND_COPYBACK),
-       
+
        /* Options for new chips with large page size. The pagesize and the
         * erasesize is determined from the extended id bytes
         */
@@ -175,7 +176,7 @@ enum
        NAND_CMD_READID = 0x90,
        NAND_CMD_ERASE2 = 0xd0,
        NAND_CMD_RESET = 0xff,
-       
+
        /* Extended commands for large page devices */
        NAND_CMD_READSTART = 0x30,
        NAND_CMD_RNDOUTSTART = 0xE0,
@@ -198,8 +199,9 @@ enum oob_formats
        NAND_OOB_NONE = 0x0,    /* no OOB data at all */
        NAND_OOB_RAW = 0x1,             /* raw OOB data (16 bytes for 512b page sizes, 64 bytes for 2048b page sizes) */
        NAND_OOB_ONLY = 0x2,    /* only OOB data */
-       NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */ 
+       NAND_OOB_SW_ECC = 0x10, /* when writing, use SW ECC (as opposed to no ECC) */
        NAND_OOB_HW_ECC = 0x20, /* when writing, use HW ECC (as opposed to no ECC) */
+       NAND_OOB_SW_ECC_KW = 0x40, /* when writing, use Marvell's Kirkwood bootrom format */
        NAND_OOB_JFFS2 = 0x100, /* when writing, use JFFS2 OOB layout */
        NAND_OOB_YAFFS2 = 0x100,/* when writing, use YAFFS2 OOB layout */
 };
@@ -210,6 +212,7 @@ extern int nand_read_page_raw(struct nand_device_s *device, u32 page, u8 *data,
 extern int nand_write_page_raw(struct nand_device_s *device, u32 page, u8 *data, u32 data_size, u8 *oob, u32 oob_size);
 extern int nand_read_status(struct nand_device_s *device, u8 *status);
 extern int nand_calculate_ecc(struct nand_device_s *device, const u8 *dat, u8 *ecc_code);
+extern int nand_calculate_ecc_kw(struct nand_device_s *device, const u8 *dat, u8 *ecc_code);
 
 extern int nand_register_commands(struct command_context_s *cmd_ctx);
 extern int nand_init(struct command_context_s *cmd_ctx);