#endif
#define CONTROL_TIMEOUT 5000 /* 5s */
-#define PAGE_SIZE 4096
+#define FLASH_PAGE_SIZE 4096
#define PB_MAX 32
#define NUM_NS_PER_S 1000000000ULL
uint32_t wait_states;
};
+static const struct command_registration esirisc_flash_command_handlers[];
+
FLASH_BANK_COMMAND_HANDLER(esirisc_flash_bank_command)
{
struct esirisc_flash_bank *esirisc_info;
bank->driver_priv = esirisc_info;
+ /* register commands using existing esirisc context */
+ register_commands(CMD_CTX, "esirisc", esirisc_flash_command_handlers);
+
return ERROR_OK;
}
if (!(control & CONTROL_WP))
return ERROR_OK;
- esirisc_flash_unlock(bank);
+ (void)esirisc_flash_unlock(bank);
control &= ~CONTROL_WP;
if (control & CONTROL_WP)
return ERROR_OK;
- esirisc_flash_unlock(bank);
+ (void)esirisc_flash_unlock(bank);
control |= CONTROL_WP;
return esirisc_flash_control(bank, CONTROL_R);
}
-static int esirisc_flash_erase(struct flash_bank *bank, int first, int last)
+static int esirisc_flash_erase(struct flash_bank *bank, unsigned int first,
+ unsigned int last)
{
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
struct target *target = bank->target;
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- esirisc_flash_disable_protect(bank);
+ (void)esirisc_flash_disable_protect(bank);
- for (int page = first; page < last; ++page) {
- uint32_t address = page * PAGE_SIZE;
+ for (unsigned int page = first; page < last; ++page) {
+ uint32_t address = page * FLASH_PAGE_SIZE;
target_write_u32(target, esirisc_info->cfg + ADDRESS, address);
}
}
- esirisc_flash_enable_protect(bank);
+ (void)esirisc_flash_enable_protect(bank);
return retval;
}
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- esirisc_flash_disable_protect(bank);
+ (void)esirisc_flash_disable_protect(bank);
target_write_u32(target, esirisc_info->cfg + ADDRESS, 0);
if (retval != ERROR_OK)
LOG_ERROR("%s: failed to mass erase", bank->name);
- esirisc_flash_enable_protect(bank);
+ (void)esirisc_flash_enable_protect(bank);
return retval;
}
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- esirisc_flash_disable_protect(bank);
+ (void)esirisc_flash_disable_protect(bank);
retval = esirisc_flash_control(bank, CONTROL_ERC);
if (retval != ERROR_OK)
LOG_ERROR("%s: failed to erase reference cell", bank->name);
- esirisc_flash_enable_protect(bank);
+ (void)esirisc_flash_enable_protect(bank);
return retval;
}
-static int esirisc_flash_protect(struct flash_bank *bank, int set, int first, int last)
-{
- struct target *target = bank->target;
-
- if (target->state != TARGET_HALTED)
- return ERROR_TARGET_NOT_HALTED;
-
- if (set)
- esirisc_flash_enable_protect(bank);
- else
- esirisc_flash_disable_protect(bank);
-
- return ERROR_OK;
-}
-
static int esirisc_flash_fill_pb(struct flash_bank *bank,
const uint8_t *buffer, uint32_t count)
{
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- esirisc_flash_disable_protect(bank);
+ (void)esirisc_flash_disable_protect(bank);
/*
* The address register is auto-incremented based on the contents of
count -= num_bytes;
}
- esirisc_flash_enable_protect(bank);
+ (void)esirisc_flash_enable_protect(bank);
return retval;
}
uint32_t value;
int retval;
- esirisc_flash_disable_protect(bank);
+ (void)esirisc_flash_disable_protect(bank);
/* initialize timing registers */
- value = TIMING0_F(esirisc_flash_num_cycles(bank, TNVH)) |
- TIMING0_R(esirisc_info->wait_states);
+ value = TIMING0_F(esirisc_flash_num_cycles(bank, TNVH))
+ | TIMING0_R(esirisc_info->wait_states);
LOG_DEBUG("TIMING0: 0x%" PRIx32, value);
target_write_u32(target, esirisc_info->cfg + TIMING0, value);
LOG_DEBUG("TIMING1: 0x%" PRIx32, value);
target_write_u32(target, esirisc_info->cfg + TIMING1, value);
- value = TIMING2_T(esirisc_flash_num_cycles(bank, 10)) |
- TIMING2_H(esirisc_flash_num_cycles(bank, 100)) |
- TIMING2_P(esirisc_flash_num_cycles(bank, TPROG));
+ value = TIMING2_T(esirisc_flash_num_cycles(bank, 10))
+ | TIMING2_H(esirisc_flash_num_cycles(bank, 100))
+ | TIMING2_P(esirisc_flash_num_cycles(bank, TPROG));
LOG_DEBUG("TIMING2: 0x%" PRIx32, value);
target_write_u32(target, esirisc_info->cfg + TIMING2, value);
if (retval != ERROR_OK)
LOG_ERROR("%s: failed to recall trim code", bank->name);
- esirisc_flash_enable_protect(bank);
+ (void)esirisc_flash_enable_protect(bank);
return retval;
}
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
- bank->num_sectors = bank->size / PAGE_SIZE;
- bank->sectors = alloc_block_array(0, PAGE_SIZE, bank->num_sectors);
-
- /*
- * Register write protection is enforced using a single protection
- * block for the entire bank. This is as good as it gets.
- */
- bank->num_prot_blocks = 1;
- bank->prot_blocks = alloc_block_array(0, bank->size, bank->num_prot_blocks);
+ bank->num_sectors = bank->size / FLASH_PAGE_SIZE;
+ bank->sectors = alloc_block_array(0, FLASH_PAGE_SIZE, bank->num_sectors);
retval = esirisc_flash_init(bank);
if (retval != ERROR_OK) {
return esirisc_flash_probe(bank);
}
-static int esirisc_flash_protect_check(struct flash_bank *bank)
+static int esirisc_flash_info(struct flash_bank *bank, struct command_invocation *cmd)
{
struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
- struct target *target = bank->target;
- uint32_t control;
-
- if (target->state != TARGET_HALTED)
- return ERROR_TARGET_NOT_HALTED;
-
- target_read_u32(target, esirisc_info->cfg + CONTROL, &control);
-
- /* single protection block (also see: esirisc_flash_probe()) */
- bank->prot_blocks[0].is_protected = !!(control & CONTROL_WP);
- return ERROR_OK;
-}
-
-static int esirisc_flash_info(struct flash_bank *bank, char *buf, int buf_size)
-{
- struct esirisc_flash_bank *esirisc_info = bank->driver_priv;
-
- snprintf(buf, buf_size,
- "%4s cfg at 0x%" PRIx32 ", clock %" PRId32 ", wait_states %" PRId32,
+ command_print_sameline(cmd,
+ "%4s cfg at 0x%" PRIx32 ", clock %" PRIu32 ", wait_states %" PRIu32,
"", /* align with first line */
esirisc_info->cfg,
esirisc_info->clock,
retval = esirisc_flash_mass_erase(bank);
- command_print(CMD_CTX, "mass erase %s",
+ command_print(CMD, "mass erase %s",
(retval == ERROR_OK) ? "successful" : "failed");
return retval;
retval = esirisc_flash_ref_erase(bank);
- command_print(CMD_CTX, "erase reference cell %s",
+ command_print(CMD, "erase reference cell %s",
(retval == ERROR_OK) ? "successful" : "failed");
return retval;
.name = "mass_erase",
.handler = handle_esirisc_flash_mass_erase_command,
.mode = COMMAND_EXEC,
- .help = "erases all pages in data memory",
+ .help = "erase all pages in data memory",
.usage = "bank_id",
},
{
.name = "ref_erase",
.handler = handle_esirisc_flash_ref_erase_command,
.mode = COMMAND_EXEC,
- .help = "erases reference cell (uncommon)",
+ .help = "erase reference cell (uncommon)",
.usage = "bank_id",
},
COMMAND_REGISTRATION_DONE
static const struct command_registration esirisc_flash_command_handlers[] = {
{
- .name = "esirisc_flash",
- .mode = COMMAND_ANY,
- .help = "eSi-RISC flash command group",
+ .name = "flash",
+ .mode = COMMAND_EXEC,
+ .help = "eSi-TSMC Flash command group",
.usage = "",
.chain = esirisc_flash_exec_command_handlers,
},
COMMAND_REGISTRATION_DONE
};
-struct flash_driver esirisc_flash = {
+const struct flash_driver esirisc_flash = {
.name = "esirisc",
- .commands = esirisc_flash_command_handlers,
.usage = "flash bank bank_id 'esirisc' base_address size_bytes 0 0 target "
"cfg_address clock_hz wait_states",
.flash_bank_command = esirisc_flash_bank_command,
.erase = esirisc_flash_erase,
- .protect = esirisc_flash_protect,
.write = esirisc_flash_write,
.read = default_flash_read,
.probe = esirisc_flash_probe,
.auto_probe = esirisc_flash_auto_probe,
.erase_check = default_flash_blank_check,
- .protect_check = esirisc_flash_protect_check,
.info = esirisc_flash_info,
+ .free_driver_priv = default_flash_free_driver_priv,
};
Code Review / openocd.git / blobdiff