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aarch64: remove armv7-a virt-to-phys code
[openocd.git] / src / target / aarch64.c
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index 09e828e0183c4ed91b75e7a10181085bb59e0fca..a2ed8b5f8297be77a0266bcf3ddbaf594e1dc2d5 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -529,7 +529,7 @@ static int aarch64_instr_write_data_r0(struct arm_dpm *dpm,
 
        retval = aarch64_exec_opcode(
                        a8->armv8_common.arm.target,
-                       0xd5330500,
+                       ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
                        &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -556,7 +556,7 @@ static int aarch64_instr_write_data_r0_64(struct arm_dpm *dpm,
 
        retval = aarch64_exec_opcode(
                        a8->armv8_common.arm.target,
-                       0xd5330400,
+                       ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0),
                        &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -577,7 +577,7 @@ static int aarch64_instr_cpsr_sync(struct arm_dpm *dpm)
 
        /* "Prefetch flush" after modifying execution status in CPSR */
        return aarch64_exec_opcode(target,
-                       ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+                       DSB_SY,
                        &dscr);
 }
 
@@ -635,7 +635,7 @@ static int aarch64_instr_read_data_r0(struct arm_dpm *dpm,
        /* write R0 to DCC */
        retval = aarch64_exec_opcode(
                        a8->armv8_common.arm.target,
-                       0xd5130400,  /* msr dbgdtr_el0, x0 */
+                       ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0),  /* msr dbgdtr_el0, x0 */
                        &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -661,7 +661,7 @@ static int aarch64_instr_read_data_r0_64(struct arm_dpm *dpm,
        /* write R0 to DCC */
        retval = aarch64_exec_opcode(
                        a8->armv8_common.arm.target,
-                       0xd5130400,  /* msr dbgdtr_el0, x0 */
+                       ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0),  /* msr dbgdtr_el0, x0 */
                        &dscr);
        if (retval != ERROR_OK)
                return retval;
@@ -690,8 +690,8 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
                default:
                        return ERROR_FAIL;
        }
-       vr += 4 * index_t;
-       cr += 4 * index_t;
+       vr += 16 * index_t;
+       cr += 16 * index_t;
 
        LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
                (unsigned) vr, (unsigned) cr);
@@ -707,9 +707,6 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 
 static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 {
-       return ERROR_OK;
-
-#if 0
        struct aarch64_common *a = dpm_to_a8(dpm);
        uint32_t cr;
 
@@ -724,13 +721,13 @@ static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
                default:
                        return ERROR_FAIL;
        }
-       cr += 4 * index_t;
+       cr += 16 * index_t;
 
        LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
 
        /* clear control register */
        return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
-#endif
+
 }
 
 static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
@@ -1140,49 +1137,45 @@ static int aarch64_resume(struct target *target, int current,
 
 static int aarch64_debug_entry(struct target *target)
 {
-       uint32_t dscr;
        int retval = ERROR_OK;
        struct aarch64_common *aarch64 = target_to_aarch64(target);
        struct armv8_common *armv8 = target_to_armv8(target);
-       uint32_t tmp;
 
        LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr);
 
-       /* REVISIT surely we should not re-read DSCR !! */
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
-       if (retval != ERROR_OK)
-               return retval;
-
        /* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
         * imprecise data aborts get discarded by issuing a Data
         * Synchronization Barrier:  ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
         */
 
-       /* Enable the ITR execution once we are in debug mode */
-       dscr |= DSCR_ITR_EN;
+       /* make sure to clear all sticky errors */
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+                       armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
        if (retval != ERROR_OK)
                return retval;
 
        /* Examine debug reason */
-       arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
-       mem_ap_read_atomic_u32(armv8->debug_ap,
-                                  armv8->debug_base + CPUV8_DBG_EDESR, &tmp);
-       if ((tmp & 0x7) == 0x4)
-               target->debug_reason = DBG_REASON_SINGLESTEP;
+       armv8_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
 
        /* save address of instruction that triggered the watchpoint? */
        if (target->debug_reason == DBG_REASON_WATCHPOINT) {
-               uint32_t wfar;
+               uint32_t tmp;
+               uint64_t wfar = 0;
 
+               retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+                               armv8->debug_base + CPUV8_DBG_WFAR1,
+                               &tmp);
+               if (retval != ERROR_OK)
+                       return retval;
+               wfar = tmp;
+               wfar = (wfar << 32);
                retval = mem_ap_read_atomic_u32(armv8->debug_ap,
                                armv8->debug_base + CPUV8_DBG_WFAR0,
-                               &wfar);
+                               &tmp);
                if (retval != ERROR_OK)
                        return retval;
-               arm_dpm_report_wfar(&armv8->dpm, wfar);
+               wfar |= tmp;
+               armv8_dpm_report_wfar(&armv8->dpm, wfar);
        }
 
        retval = armv8_dpm_read_current_registers(&armv8->dpm);
@@ -1239,10 +1232,8 @@ static int aarch64_post_debug_entry(struct target *target)
        LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
        aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
-#if 0
        if (armv8->armv8_mmu.armv8_cache.ctype == -1)
                armv8_identify_cache(target);
-#endif
 
        armv8->armv8_mmu.mmu_enabled =
                        (aarch64->system_control_reg & 0x1U) ? 1 : 0;
@@ -1384,8 +1375,7 @@ static int aarch64_set_breakpoint(struct target *target,
 
        } else if (breakpoint->type == BKPT_SOFT) {
                uint8_t code[4];
-               buf_set_u32(code, 0, 32, 0xD4400000);
-
+               buf_set_u32(code, 0, 32, ARMV8_BKPT(0x11));
                retval = target_read_memory(target,
                                breakpoint->address & 0xFFFFFFFFFFFFFFFE,
                                breakpoint->length, 1,
@@ -1581,6 +1571,16 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_i].control);
                        if (retval != ERROR_OK)
                                return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
                        if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
                                LOG_DEBUG("Invalid BRP number in breakpoint");
                                return ERROR_OK;
@@ -1595,6 +1595,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_j].control);
                        if (retval != ERROR_OK)
                                return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
+                                       (uint32_t)brp_list[brp_j].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn,
+                                       (uint32_t)brp_list[brp_j].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+
                        breakpoint->linked_BRP = 0;
                        breakpoint->set = 0;
                        return ERROR_OK;
@@ -1620,6 +1631,12 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_i].value);
                        if (retval != ERROR_OK)
                                return retval;
+
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
                        breakpoint->set = 0;
                        return ERROR_OK;
                }
@@ -2606,12 +2623,8 @@ static int aarch64_virt2phys(struct target *target, target_addr_t virt,
                if (retval != ERROR_OK)
                        goto done;
                *phys = ret;
-       } else {/*  use this method if armv8->memory_ap not selected
-                *  mmu must be enable in order to get a correct translation */
-               retval = aarch64_mmu_modify(target, 1);
-               if (retval != ERROR_OK)
-                       goto done;
-               retval = armv8_mmu_translate_va_pa(target, virt,  phys, 1);
+       } else {
+               LOG_ERROR("AAR64 processor not support translate va to pa");
        }
 done:
        return retval;
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