if (aarch64->system_control_reg != aarch64->system_control_reg_curr) {
aarch64->system_control_reg_curr = aarch64->system_control_reg;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg);
+ /* LOG_INFO("cp15_control_reg: %8.8" PRIx32, cortex_v8->cp15_control_reg); */
+
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 1, /* op1, op2 */
+ 0, 0, /* CRn, CRm */
+ aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
}
-
return retval;
}
int retval = ERROR_OK;
if (enable) {
- /* if mmu enabled at target stop and mmu not enable */
+ /* if mmu enabled at target stop and mmu not enable */
if (!(aarch64->system_control_reg & 0x1U)) {
LOG_ERROR("trying to enable mmu on target stopped with mmu disable");
return ERROR_FAIL;
}
if (!(aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr |= 0x1U;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg_curr);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
}
} else {
if (aarch64->system_control_reg_curr & 0x4U) {
}
if ((aarch64->system_control_reg_curr & 0x1U)) {
aarch64->system_control_reg_curr &= ~0x1U;
- retval = aarch64_instr_write_data_r0(armv8->arm.dpm,
- 0xd5181000,
- aarch64->system_control_reg_curr);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.msr(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ aarch64->system_control_reg_curr);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ break;
+ }
}
}
return retval;
if (dscr & DSCR_DTR_RX_FULL) {
LOG_ERROR("DSCR_DTR_RX_FULL, dscr 0x%08" PRIx32, dscr);
/* Clear DCCRX */
- retval = aarch64_exec_opcode(
- a8->armv8_common.arm.target,
- 0xd5130400,
- &dscr);
+ retval = mem_ap_read_u32(a8->armv8_common.debug_ap,
+ a8->armv8_common.debug_base + CPUV8_DBG_DTRRX, &dscr);
+ if (retval != ERROR_OK)
+ return retval;
+
+ /* Clear sticky error */
+ retval = mem_ap_write_u32(a8->armv8_common.debug_ap,
+ a8->armv8_common.debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
if (retval != ERROR_OK)
return retval;
}
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5330500,
+ ARMV8_MRS(SYSTEM_DBG_DTRRX_EL0, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5330400,
+ ARMV8_MRS(SYSTEM_DBG_DBGDTR_EL0, 0),
&dscr);
if (retval != ERROR_OK)
return retval;
/* "Prefetch flush" after modifying execution status in CPSR */
return aarch64_exec_opcode(target,
- ARMV4_5_MCR(15, 0, 0, 7, 5, 4),
+ DSB_SY,
&dscr);
}
/* write R0 to DCC */
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5130400, /* msr dbgdtr_el0, x0 */
+ ARMV8_MSR_GP(SYSTEM_DBG_DTRTX_EL0, 0), /* msr dbgdtr_el0, x0 */
&dscr);
if (retval != ERROR_OK)
return retval;
/* write R0 to DCC */
retval = aarch64_exec_opcode(
a8->armv8_common.arm.target,
- 0xd5130400, /* msr dbgdtr_el0, x0 */
+ ARMV8_MSR_GP(SYSTEM_DBG_DBGDTR_EL0, 0), /* msr dbgdtr_el0, x0 */
&dscr);
if (retval != ERROR_OK)
return retval;
default:
return ERROR_FAIL;
}
- vr += 4 * index_t;
- cr += 4 * index_t;
+ vr += 16 * index_t;
+ cr += 16 * index_t;
LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
(unsigned) vr, (unsigned) cr);
static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
{
- return ERROR_OK;
-
-#if 0
struct aarch64_common *a = dpm_to_a8(dpm);
uint32_t cr;
default:
return ERROR_FAIL;
}
- cr += 4 * index_t;
+ cr += 16 * index_t;
LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
/* clear control register */
return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
-#endif
+
}
-static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
+static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
{
struct arm_dpm *dpm = &a8->armv8_common.dpm;
int retval;
uint32_t dscr;
struct armv8_common *armv8 = target_to_armv8(target);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, &dscr);
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, 1);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0, &dscr);
-
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, &dscr);
+ /* enable CTI*/
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, 6);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x140, &dscr);
+ armv8->cti_base + CTI_CTR, 1);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, 5);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa0, &dscr);
+ armv8->cti_base + CTI_GATE, 3);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, 2);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0xa4, &dscr);
+ armv8->cti_base + CTI_OUTEN0, 1);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, 4);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x20, &dscr);
+ armv8->cti_base + CTI_OUTEN1, 2);
+ if (retval != ERROR_OK)
+ return retval;
/*
- * enter halting debug mode
+ * add HDE in halting debug mode
*/
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
-# /* STATUS */
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x134, &dscr);
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DSCR, dscr | DSCR_HDE);
+ if (retval != ERROR_OK)
+ return retval;
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, &dscr);
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, 1);
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, &dscr);
+ armv8->cti_base + CTI_APPPULSE, 1);
+ if (retval != ERROR_OK)
+ return retval;
+
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->cti_base + CTI_INACK, 1);
+ if (retval != ERROR_OK)
+ return retval;
long long then = timeval_ms();
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if ((dscr & DSCR_CORE_HALTED) != 0)
+ if ((dscr & DSCRV8_HALT_MASK) != 0)
break;
if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for halt");
LOG_ERROR("DSCR InstrCompl must be set before leaving debug!");
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, dscr & ~DSCR_ITR_EN);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DRCR, DRCR_RESTART |
- DRCR_CLEAR_EXCEPTIONS);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x10, 1);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x10000 + 0x1c, 2);
+ armv8->cti_base + CTI_APPPULSE, 2);
if (retval != ERROR_OK)
return retval;
armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
if (retval != ERROR_OK)
return retval;
- if ((dscr & DSCR_CORE_RESTARTED) != 0)
+ if ((dscr & DSCR_HDE) != 0)
break;
if (timeval_ms() > then + 1000) {
LOG_ERROR("Timeout waiting for resume");
if (!debug_execution) {
target->state = TARGET_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_RESUMED);
- LOG_DEBUG("target resumed at 0x%" PRIu64, addr);
+ LOG_DEBUG("target resumed at 0x%" PRIx64, addr);
} else {
target->state = TARGET_DEBUG_RUNNING;
target_call_event_callbacks(target, TARGET_EVENT_DEBUG_RESUMED);
- LOG_DEBUG("target debug resumed at 0x%" PRIu64, addr);
+ LOG_DEBUG("target debug resumed at 0x%" PRIx64, addr);
}
return ERROR_OK;
static int aarch64_debug_entry(struct target *target)
{
- uint32_t dscr;
int retval = ERROR_OK;
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = target_to_armv8(target);
- uint32_t tmp;
LOG_DEBUG("dscr = 0x%08" PRIx32, aarch64->cpudbg_dscr);
- /* REVISIT surely we should not re-read DSCR !! */
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, &dscr);
- if (retval != ERROR_OK)
- return retval;
-
/* REVISIT see A8 TRM 12.11.4 steps 2..3 -- make sure that any
* imprecise data aborts get discarded by issuing a Data
* Synchronization Barrier: ARMV4_5_MCR(15, 0, 0, 7, 10, 4).
*/
- /* Enable the ITR execution once we are in debug mode */
- dscr |= DSCR_ITR_EN;
+ /* make sure to clear all sticky errors */
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DSCR, dscr);
+ armv8->debug_base + CPUV8_DBG_DRCR, DRCR_CSE);
if (retval != ERROR_OK)
return retval;
/* Examine debug reason */
- arm_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
- mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_EDESR, &tmp);
- if ((tmp & 0x7) == 0x4)
- target->debug_reason = DBG_REASON_SINGLESTEP;
+ armv8_dpm_report_dscr(&armv8->dpm, aarch64->cpudbg_dscr);
/* save address of instruction that triggered the watchpoint? */
if (target->debug_reason == DBG_REASON_WATCHPOINT) {
- uint32_t wfar;
+ uint32_t tmp;
+ uint64_t wfar = 0;
+ retval = mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_WFAR1,
+ &tmp);
+ if (retval != ERROR_OK)
+ return retval;
+ wfar = tmp;
+ wfar = (wfar << 32);
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_WFAR0,
- &wfar);
+ &tmp);
if (retval != ERROR_OK)
return retval;
- arm_dpm_report_wfar(&armv8->dpm, wfar);
+ wfar |= tmp;
+ armv8_dpm_report_wfar(&armv8->dpm, wfar);
}
retval = armv8_dpm_read_current_registers(&armv8->dpm);
{
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
- struct armv8_mmu_common *armv8_mmu = &armv8->armv8_mmu;
- uint32_t sctlr_el1 = 0;
int retval;
mem_ap_write_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
- retval = aarch64_instr_read_data_r0(armv8->arm.dpm,
- 0xd5381000, &sctlr_el1);
- if (retval != ERROR_OK)
- return retval;
-
- LOG_DEBUG("sctlr_el1 = %#8.8x", sctlr_el1);
- aarch64->system_control_reg = sctlr_el1;
- aarch64->system_control_reg_curr = sctlr_el1;
- aarch64->curr_mode = armv8->arm.core_mode;
-
- armv8_mmu->mmu_enabled = sctlr_el1 & 0x1U ? 1 : 0;
- armv8_mmu->armv8_cache.d_u_cache_enabled = sctlr_el1 & 0x4U ? 1 : 0;
- armv8_mmu->armv8_cache.i_cache_enabled = sctlr_el1 & 0x1000U ? 1 : 0;
+ armv8->debug_base + CPUV8_DBG_DRCR, 1<<2);
+ switch (armv8->arm.core_mode) {
+ case ARMV8_64_EL0T:
+ case ARMV8_64_EL1T:
+ case ARMV8_64_EL1H:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 0, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL2T:
+ case ARMV8_64_EL2H:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 4, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ case ARMV8_64_EL3H:
+ case ARMV8_64_EL3T:
+ retval = armv8->arm.mrs(target, 3, /*op 0*/
+ 6, 0, /* op1, op2 */
+ 1, 0, /* CRn, CRm */
+ &aarch64->system_control_reg);
+ if (retval != ERROR_OK)
+ return retval;
+ break;
+ default:
+ LOG_DEBUG("unknow cpu state 0x%x" PRIx32, armv8->arm.core_state);
+ }
+ LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
+ aarch64->system_control_reg_curr = aarch64->system_control_reg;
-#if 0
if (armv8->armv8_mmu.armv8_cache.ctype == -1)
armv8_identify_cache(target);
-#endif
+ armv8->armv8_mmu.mmu_enabled =
+ (aarch64->system_control_reg & 0x1U) ? 1 : 0;
+ armv8->armv8_mmu.armv8_cache.d_u_cache_enabled =
+ (aarch64->system_control_reg & 0x4U) ? 1 : 0;
+ armv8->armv8_mmu.armv8_cache.i_cache_enabled =
+ (aarch64->system_control_reg & 0x1000U) ? 1 : 0;
+ aarch64->curr_mode = armv8->arm.core_mode;
return ERROR_OK;
}
} else if (breakpoint->type == BKPT_SOFT) {
uint8_t code[4];
- buf_set_u32(code, 0, 32, 0xD4400000);
-
+ buf_set_u32(code, 0, 32, ARMV8_BKPT(0x11));
retval = target_read_memory(target,
breakpoint->address & 0xFFFFFFFFFFFFFFFE,
breakpoint->length, 1,
breakpoint->set = brp_i + 1;
control = ((matchmode & 0x7) << 20)
+ | (1 << 13)
| (byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_i].used = 1;
brp_list[brp_i].value = (breakpoint->asid);
brp_list[brp_i].control = control;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
brp_list[brp_1].value = (breakpoint->asid);
brp_list[brp_1].control = control_CTX;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 * brp_list[brp_1].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_1].BRPn,
brp_list[brp_1].value);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 4 * brp_list[brp_1].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_1].BRPn,
brp_list[brp_1].control);
if (retval != ERROR_OK)
return retval;
control_IVA = ((IVA_machmode & 0x7) << 20)
| (brp_1 << 16)
+ | (1 << 13)
| (IVA_byte_addr_select << 5)
| (3 << 1) | 1;
brp_list[brp_2].used = 1;
- brp_list[brp_2].value = (breakpoint->address & 0xFFFFFFFC);
+ brp_list[brp_2].value = breakpoint->address & 0xFFFFFFFFFFFFFFFC;
brp_list[brp_2].control = control_IVA;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 * brp_list[brp_2].BRPn,
- brp_list[brp_2].value);
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_2].BRPn,
+ brp_list[brp_2].value & 0xFFFFFFFF);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 4 * brp_list[brp_2].BRPn,
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_2].BRPn,
+ brp_list[brp_2].value >> 32);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_2].BRPn,
brp_list[brp_2].control);
if (retval != ERROR_OK)
return retval;
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+ (uint32_t)brp_list[brp_i].value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ (uint32_t)brp_list[brp_i].value);
+ if (retval != ERROR_OK)
+ return retval;
if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
LOG_DEBUG("Invalid BRP number in breakpoint");
return ERROR_OK;
brp_list[brp_j].control);
if (retval != ERROR_OK)
return retval;
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
+ (uint32_t)brp_list[brp_j].value);
+ if (retval != ERROR_OK)
+ return retval;
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn,
+ (uint32_t)brp_list[brp_j].value);
+ if (retval != ERROR_OK)
+ return retval;
+
breakpoint->linked_BRP = 0;
breakpoint->set = 0;
return ERROR_OK;
brp_list[brp_i].value = 0;
brp_list[brp_i].control = 0;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BCR_BASE + 4 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BCR_BASE + 16 * brp_list[brp_i].BRPn,
brp_list[brp_i].control);
if (retval != ERROR_OK)
return retval;
retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
- + CPUV8_DBG_BVR_BASE + 4 * brp_list[brp_i].BRPn,
+ + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
brp_list[brp_i].value);
if (retval != ERROR_OK)
return retval;
+
+ retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+ + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+ (uint32_t)brp_list[brp_i].value);
+ if (retval != ERROR_OK)
+ return retval;
breakpoint->set = 0;
return ERROR_OK;
}
* wrong addresses will be invalidated!
*
* For both ICache and DCache, walk all cache lines in the
- * address range. Cortex-A8 has fixed 64 byte line length.
+ * address range. Cortex-A has fixed 64 byte line length.
*
* REVISIT per ARMv7, these may trigger watchpoints ...
*/
* with MVA to PoU
* MCR p15, 0, r0, c7, c5, 1
*/
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
+ for (uint32_t cacheline = 0;
+ cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
- cacheline);
+ ARMV8_MSR_GP(SYSTEM_ICIVAU, 0),
+ address + cacheline);
if (retval != ERROR_OK)
return retval;
}
* with MVA to PoC
* MCR p15, 0, r0, c7, c6, 1
*/
- for (uint32_t cacheline = address;
- cacheline < address + size * count;
+ for (uint32_t cacheline = 0;
+ cacheline < size * count;
cacheline += 64) {
retval = dpm->instr_write_data_r0(dpm,
- ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
- cacheline);
+ ARMV8_MSR_GP(SYSTEM_DCCVAU, 0),
+ address + cacheline);
if (retval != ERROR_OK)
return retval;
}
struct aarch64_common *aarch64 = target_to_aarch64(target);
struct armv8_common *armv8 = &aarch64->armv8_common;
struct adiv5_dap *swjdp = armv8->arm.dap;
- int retval = ERROR_OK;
- uint32_t pfr, debug, ctypr, ttypr, cpuid;
int i;
+ int retval = ERROR_OK;
+ uint64_t debug, ttypr;
+ uint32_t cpuid;
+ uint32_t tmp0, tmp1;
+ debug = ttypr = cpuid = 0;
/* We do one extra read to ensure DAP is configured,
* we call ahbap_debugport_init(swjdp) instead
&armv8->debug_base, &coreidx);
if (retval != ERROR_OK)
return retval;
- LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
- coreidx, armv8->debug_base);
+ LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32
+ " apid: %08" PRIx32, coreidx, armv8->debug_base, apid);
} else
armv8->debug_base = target->dbgbase;
retval = mem_ap_write_atomic_u32(armv8->debug_ap,
armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
if (retval != ERROR_OK) {
- LOG_DEBUG("Examine %s failed", "oslock");
+ LOG_DEBUG("LOCK debug access fail");
return retval;
}
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x88, &cpuid);
- LOG_DEBUG("0x88 = %x", cpuid);
-
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x314, &cpuid);
- LOG_DEBUG("0x314 = %x", cpuid);
-
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + 0x310, &cpuid);
- LOG_DEBUG("0x310 = %x", cpuid);
- if (retval != ERROR_OK)
- return retval;
-
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUDBG_CPUID, &cpuid);
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_OSLAR, 0);
if (retval != ERROR_OK) {
- LOG_DEBUG("Examine %s failed", "CPUID");
+ LOG_DEBUG("Examine %s failed", "oslock");
return retval;
}
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUDBG_CTYPR, &ctypr);
+ armv8->debug_base + CPUV8_DBG_MAINID0, &cpuid);
if (retval != ERROR_OK) {
- LOG_DEBUG("Examine %s failed", "CTYPR");
+ LOG_DEBUG("Examine %s failed", "CPUID");
return retval;
}
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + CPUDBG_TTYPR, &ttypr);
+ armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0);
+ retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1);
if (retval != ERROR_OK) {
- LOG_DEBUG("Examine %s failed", "TTYPR");
+ LOG_DEBUG("Examine %s failed", "Memory Model Type");
return retval;
}
+ ttypr |= tmp1;
+ ttypr = (ttypr << 32) | tmp0;
retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + ID_AA64PFR0_EL1, &pfr);
- if (retval != ERROR_OK) {
- LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
- return retval;
- }
- retval = mem_ap_read_atomic_u32(armv8->debug_ap,
- armv8->debug_base + ID_AA64DFR0_EL1, &debug);
+ armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp0);
+ retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+ armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp1);
if (retval != ERROR_OK) {
LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
return retval;
}
+ debug |= tmp1;
+ debug = (debug << 32) | tmp0;
LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
- LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
- LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
- LOG_DEBUG("ID_AA64PFR0_EL1 = 0x%08" PRIx32, pfr);
- LOG_DEBUG("ID_AA64DFR0_EL1 = 0x%08" PRIx32, debug);
+ LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
+ LOG_DEBUG("debug = 0x%08" PRIx64, debug);
+
+ if (target->ctibase == 0) {
+ /* assume a v8 rom table layout */
+ armv8->cti_base = target->ctibase = armv8->debug_base + 0x10000;
+ LOG_INFO("Target ctibase is not set, assuming 0x%0" PRIx32, target->ctibase);
+ } else
+ armv8->cti_base = target->ctibase;
+
+ retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+ armv8->cti_base + CTI_UNLOCK , 0xC5ACCE55);
+ if (retval != ERROR_OK)
+ return retval;
+
armv8->arm.core_type = ARM_MODE_MON;
- armv8->arm.core_state = ARM_STATE_AARCH64;
retval = aarch64_dpm_setup(aarch64, debug);
if (retval != ERROR_OK)
return retval;
/* Setup Breakpoint Register Pairs */
- aarch64->brp_num = ((debug >> 12) & 0x0F) + 1;
- aarch64->brp_num_context = ((debug >> 28) & 0x0F) + 1;
-
- /* hack - no context bpt support yet */
- aarch64->brp_num_context = 0;
-
+ aarch64->brp_num = (uint32_t)((debug >> 12) & 0x0F) + 1;
+ aarch64->brp_num_context = (uint32_t)((debug >> 28) & 0x0F) + 1;
aarch64->brp_num_available = aarch64->brp_num;
aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
for (i = 0; i < aarch64->brp_num; i++) {
if (retval != ERROR_OK)
goto done;
*phys = ret;
- } else {/* use this method if armv8->memory_ap not selected
- * mmu must be enable in order to get a correct translation */
- retval = aarch64_mmu_modify(target, 1);
- if (retval != ERROR_OK)
- goto done;
- retval = armv8_mmu_translate_va_pa(target, virt, phys, 1);
+ } else {
+ LOG_ERROR("AAR64 processor not support translate va to pa");
}
done:
return retval;
Code Review / openocd.git / blobdiff