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aarch64: use correct A64 instructions for cache handling
[openocd.git] / src / target / aarch64.c
diff --git a/src/target/aarch64.c b/src/target/aarch64.c
index ef73afd7e84f4c249f28fe7f1c0ae7a333500e31..d76da83f46f505cb4a3ce606485dd919cf066e76 100644 (file)
--- a/src/target/aarch64.c
+++ b/src/target/aarch64.c
@@ -690,8 +690,8 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
                default:
                        return ERROR_FAIL;
        }
-       vr += 4 * index_t;
-       cr += 4 * index_t;
+       vr += 16 * index_t;
+       cr += 16 * index_t;
 
        LOG_DEBUG("A8: bpwp enable, vr %08x cr %08x",
                (unsigned) vr, (unsigned) cr);
@@ -707,9 +707,6 @@ static int aarch64_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
 
 static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
 {
-       return ERROR_OK;
-
-#if 0
        struct aarch64_common *a = dpm_to_a8(dpm);
        uint32_t cr;
 
@@ -724,16 +721,16 @@ static int aarch64_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
                default:
                        return ERROR_FAIL;
        }
-       cr += 4 * index_t;
+       cr += 16 * index_t;
 
        LOG_DEBUG("A: bpwp disable, cr %08x", (unsigned) cr);
 
        /* clear control register */
        return aarch64_dap_write_memap_register_u32(dpm->arm->target, cr, 0);
-#endif
+
 }
 
-static int aarch64_dpm_setup(struct aarch64_common *a8, uint32_t debug)
+static int aarch64_dpm_setup(struct aarch64_common *a8, uint64_t debug)
 {
        struct arm_dpm *dpm = &a8->armv8_common.dpm;
        int retval;
@@ -1235,10 +1232,8 @@ static int aarch64_post_debug_entry(struct target *target)
        LOG_DEBUG("System_register: %8.8" PRIx32, aarch64->system_control_reg);
        aarch64->system_control_reg_curr = aarch64->system_control_reg;
 
-#if 0
        if (armv8->armv8_mmu.armv8_cache.ctype == -1)
                armv8_identify_cache(target);
-#endif
 
        armv8->armv8_mmu.mmu_enabled =
                        (aarch64->system_control_reg & 0x1U) ? 1 : 0;
@@ -1576,6 +1571,16 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_i].control);
                        if (retval != ERROR_OK)
                                return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
                        if ((brp_j < 0) || (brp_j >= aarch64->brp_num)) {
                                LOG_DEBUG("Invalid BRP number in breakpoint");
                                return ERROR_OK;
@@ -1590,6 +1595,17 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_j].control);
                        if (retval != ERROR_OK)
                                return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 16 * brp_list[brp_j].BRPn,
+                                       (uint32_t)brp_list[brp_j].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_j].BRPn,
+                                       (uint32_t)brp_list[brp_j].value);
+                       if (retval != ERROR_OK)
+                               return retval;
+
                        breakpoint->linked_BRP = 0;
                        breakpoint->set = 0;
                        return ERROR_OK;
@@ -1615,6 +1631,12 @@ static int aarch64_unset_breakpoint(struct target *target, struct breakpoint *br
                                        brp_list[brp_i].value);
                        if (retval != ERROR_OK)
                                return retval;
+
+                       retval = aarch64_dap_write_memap_register_u32(target, armv8->debug_base
+                                       + CPUV8_DBG_BVR_BASE + 4 + 16 * brp_list[brp_i].BRPn,
+                                       (uint32_t)brp_list[brp_i].value);
+                       if (retval != ERROR_OK)
+                               return retval;
                        breakpoint->set = 0;
                        return ERROR_OK;
                }
@@ -2213,7 +2235,7 @@ static int aarch64_write_phys_memory(struct target *target,
                 * wrong addresses will be invalidated!
                 *
                 * For both ICache and DCache, walk all cache lines in the
-                * address range. Cortex-A8 has fixed 64 byte line length.
+                * address range. Cortex-A has fixed 64 byte line length.
                 *
                 * REVISIT per ARMv7, these may trigger watchpoints ...
                 */
@@ -2224,12 +2246,12 @@ static int aarch64_write_phys_memory(struct target *target,
                         * with MVA to PoU
                         *      MCR p15, 0, r0, c7, c5, 1
                         */
-                       for (uint32_t cacheline = address;
-                               cacheline < address + size * count;
+                       for (uint32_t cacheline = 0;
+                               cacheline < size * count;
                                cacheline += 64) {
                                retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
-                                               cacheline);
+                                               ARMV8_MSR_GP(SYSTEM_ICIVAU, 0),
+                                               address + cacheline);
                                if (retval != ERROR_OK)
                                        return retval;
                        }
@@ -2241,12 +2263,12 @@ static int aarch64_write_phys_memory(struct target *target,
                         * with MVA to PoC
                         *      MCR p15, 0, r0, c7, c6, 1
                         */
-                       for (uint32_t cacheline = address;
-                               cacheline < address + size * count;
+                       for (uint32_t cacheline = 0;
+                               cacheline < size * count;
                                cacheline += 64) {
                                retval = dpm->instr_write_data_r0(dpm,
-                                               ARMV4_5_MCR(15, 0, 0, 7, 6, 1),
-                                               cacheline);
+                                               ARMV8_MSR_GP(SYSTEM_DCCVAU, 0),
+                                               address + cacheline);
                                if (retval != ERROR_OK)
                                        return retval;
                        }
@@ -2346,9 +2368,12 @@ static int aarch64_examine_first(struct target *target)
        struct aarch64_common *aarch64 = target_to_aarch64(target);
        struct armv8_common *armv8 = &aarch64->armv8_common;
        struct adiv5_dap *swjdp = armv8->arm.dap;
-       int retval = ERROR_OK;
-       uint32_t pfr, debug, ctypr, ttypr, cpuid;
        int i;
+       int retval = ERROR_OK;
+       uint64_t debug, ttypr;
+       uint32_t cpuid;
+       uint32_t tmp0, tmp1;
+       debug = ttypr = cpuid = 0;
 
        /* We do one extra read to ensure DAP is configured,
         * we call ahbap_debugport_init(swjdp) instead
@@ -2399,91 +2424,79 @@ static int aarch64_examine_first(struct target *target)
                                &armv8->debug_base, &coreidx);
                if (retval != ERROR_OK)
                        return retval;
-               LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32,
-                         coreidx, armv8->debug_base);
+               LOG_DEBUG("Detected core %" PRId32 " dbgbase: %08" PRIx32
+                               " apid: %08" PRIx32, coreidx, armv8->debug_base, apid);
        } else
                armv8->debug_base = target->dbgbase;
 
-       LOG_DEBUG("Target ctibase is 0x%x", target->ctibase);
-       if (target->ctibase == 0)
-               armv8->cti_base = target->ctibase = armv8->debug_base + 0x1000;
-       else
-               armv8->cti_base = target->ctibase;
-
        retval = mem_ap_write_atomic_u32(armv8->debug_ap,
                        armv8->debug_base + CPUV8_DBG_LOCKACCESS, 0xC5ACCE55);
        if (retval != ERROR_OK) {
-               LOG_DEBUG("Examine %s failed", "oslock");
+               LOG_DEBUG("LOCK debug access fail");
                return retval;
        }
 
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x88, &cpuid);
-       LOG_DEBUG("0x88 = %x", cpuid);
-
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x314, &cpuid);
-       LOG_DEBUG("0x314 = %x", cpuid);
-
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + 0x310, &cpuid);
-       LOG_DEBUG("0x310 = %x", cpuid);
-       if (retval != ERROR_OK)
-               return retval;
-
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUDBG_CPUID, &cpuid);
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + CPUV8_DBG_OSLAR, 0);
        if (retval != ERROR_OK) {
-               LOG_DEBUG("Examine %s failed", "CPUID");
+               LOG_DEBUG("Examine %s failed", "oslock");
                return retval;
        }
 
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUDBG_CTYPR, &ctypr);
+                       armv8->debug_base + CPUV8_DBG_MAINID0, &cpuid);
        if (retval != ERROR_OK) {
-               LOG_DEBUG("Examine %s failed", "CTYPR");
+               LOG_DEBUG("Examine %s failed", "CPUID");
                return retval;
        }
 
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + CPUDBG_TTYPR, &ttypr);
+                       armv8->debug_base + CPUV8_DBG_MEMFEATURE0, &tmp0);
+       retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + CPUV8_DBG_MEMFEATURE0 + 4, &tmp1);
        if (retval != ERROR_OK) {
-               LOG_DEBUG("Examine %s failed", "TTYPR");
+               LOG_DEBUG("Examine %s failed", "Memory Model Type");
                return retval;
        }
+       ttypr |= tmp1;
+       ttypr = (ttypr << 32) | tmp0;
 
        retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + ID_AA64PFR0_EL1, &pfr);
-       if (retval != ERROR_OK) {
-               LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
-               return retval;
-       }
-       retval = mem_ap_read_atomic_u32(armv8->debug_ap,
-                       armv8->debug_base + ID_AA64DFR0_EL1, &debug);
+                       armv8->debug_base + CPUV8_DBG_DBGFEATURE0, &tmp0);
+       retval += mem_ap_read_atomic_u32(armv8->debug_ap,
+                       armv8->debug_base + CPUV8_DBG_DBGFEATURE0 + 4, &tmp1);
        if (retval != ERROR_OK) {
                LOG_DEBUG("Examine %s failed", "ID_AA64DFR0_EL1");
                return retval;
        }
+       debug |= tmp1;
+       debug = (debug << 32) | tmp0;
 
        LOG_DEBUG("cpuid = 0x%08" PRIx32, cpuid);
-       LOG_DEBUG("ctypr = 0x%08" PRIx32, ctypr);
-       LOG_DEBUG("ttypr = 0x%08" PRIx32, ttypr);
-       LOG_DEBUG("ID_AA64PFR0_EL1 = 0x%08" PRIx32, pfr);
-       LOG_DEBUG("ID_AA64DFR0_EL1 = 0x%08" PRIx32, debug);
+       LOG_DEBUG("ttypr = 0x%08" PRIx64, ttypr);
+       LOG_DEBUG("debug = 0x%08" PRIx64, debug);
+
+       if (target->ctibase == 0) {
+               /* assume a v8 rom table layout */
+               armv8->cti_base = target->ctibase = armv8->debug_base + 0x10000;
+               LOG_INFO("Target ctibase is not set, assuming 0x%0" PRIx32, target->ctibase);
+       } else
+               armv8->cti_base = target->ctibase;
+
+       retval = mem_ap_write_atomic_u32(armv8->debug_ap,
+                       armv8->cti_base + CTI_UNLOCK , 0xC5ACCE55);
+       if (retval != ERROR_OK)
+               return retval;
+
 
        armv8->arm.core_type = ARM_MODE_MON;
-       armv8->arm.core_state = ARM_STATE_AARCH64;
        retval = aarch64_dpm_setup(aarch64, debug);
        if (retval != ERROR_OK)
                return retval;
 
        /* Setup Breakpoint Register Pairs */
-       aarch64->brp_num = ((debug >> 12) & 0x0F) + 1;
-       aarch64->brp_num_context = ((debug >> 28) & 0x0F) + 1;
-
-       /* hack - no context bpt support yet */
-       aarch64->brp_num_context = 0;
-
+       aarch64->brp_num = (uint32_t)((debug >> 12) & 0x0F) + 1;
+       aarch64->brp_num_context = (uint32_t)((debug >> 28) & 0x0F) + 1;
        aarch64->brp_num_available = aarch64->brp_num;
        aarch64->brp_list = calloc(aarch64->brp_num, sizeof(struct aarch64_brp));
        for (i = 0; i < aarch64->brp_num; i++) {
@@ -2601,12 +2614,8 @@ static int aarch64_virt2phys(struct target *target, target_addr_t virt,
                if (retval != ERROR_OK)
                        goto done;
                *phys = ret;
-       } else {/*  use this method if armv8->memory_ap not selected
-                *  mmu must be enable in order to get a correct translation */
-               retval = aarch64_mmu_modify(target, 1);
-               if (retval != ERROR_OK)
-                       goto done;
-               retval = armv8_mmu_translate_va_pa(target, virt,  phys, 1);
+       } else {
+               LOG_ERROR("AAR64 processor not support translate va to pa");
        }
 done:
        return retval;
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