cortex a8: only physical read/write's are available when target is running

[openocd.git] / src / target / adi_v5_jtag.c

diff --git a/src/target/adi_v5_jtag.c b/src/target/adi_v5_jtag.c
index d59465bee04e7509e390465efeaedb89785e2657..0a374bea82d500d9134141d718ca3fd9881bf5ef 100644 (file)
--- a/src/target/adi_v5_jtag.c
+++ b/src/target/adi_v5_jtag.c
@@ -87,7 +87,6 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
        struct scan_field fields[2];
        uint8_t out_addr_buf;
 
-       jtag_set_end_state(TAP_IDLE);
        arm_jtag_set_instr(jtag_info, instr, NULL, TAP_IDLE);
 
        /* Scan out a read or write operation using some DP or AP register.
@@ -121,7 +120,7 @@ int adi_jtag_dp_scan(struct adiv5_dap *dap,
                jtag_add_runtest(dap->memaccess_tck,
                                TAP_IDLE);
 
-       return jtag_get_error();
+       return ERROR_OK;
 }
 
 /**
@@ -260,7 +259,11 @@ static int jtagdp_transaction_endcheck(struct adiv5_dap *dap)
                LOG_DEBUG("jtag-dp: CTRL/STAT error, 0x%" PRIx32, ctrlstat);
                /* Check power to debug regions */
                if ((ctrlstat & 0xf0000000) != 0xf0000000)
-                        ahbap_debugport_init(dap);
+               {
+                       retval = ahbap_debugport_init(dap);
+                       if (retval != ERROR_OK)
+                               return retval;
+               }
                else
                {
                        uint32_t mem_ap_csw, mem_ap_tar;
@@ -331,7 +334,6 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
        struct scan_field fields[1];
 
        /* This is a standard JTAG operation -- no DAP tweakage */
-       jtag_set_end_state(TAP_IDLE);
        retval = arm_jtag_set_instr(jtag_info, JTAG_DP_IDCODE, NULL, TAP_IDLE);
        if (retval != ERROR_OK)
                return retval;
@@ -341,14 +343,11 @@ static int jtag_idcode_q_read(struct adiv5_dap *dap,
        fields[0].in_value = (void *) data;
 
        jtag_add_dr_scan(jtag_info->tap, 1, fields, TAP_IDLE);
-       retval = jtag_get_error();
-       if (retval != ERROR_OK)
-               return retval;
 
        jtag_add_callback(arm_le_to_h_u32,
                        (jtag_callback_data_t) data);
 
-       return retval;
+       return ERROR_OK;
 }
 
 static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
@@ -368,15 +367,15 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
 /** Select the AP register bank matching bits 7:4 of reg. */
 static int jtag_ap_q_bankselect(struct adiv5_dap *dap, unsigned reg)
 {
-       uint32_t select = reg & 0x000000F0;
+       uint32_t select_ap_bank = reg & 0x000000F0;
 
-       if (select == dap->ap_bank_value)
+       if (select_ap_bank == dap->ap_bank_value)
                return ERROR_OK;
-       dap->ap_bank_value = select;
+       dap->ap_bank_value = select_ap_bank;
 
-       select |= dap->apsel;
+       select_ap_bank |= dap->apsel;
 
-       return jtag_dp_q_write(dap, DP_SELECT, select);
+       return jtag_dp_q_write(dap, DP_SELECT, select_ap_bank);
 }
 
 static int jtag_ap_q_read(struct adiv5_dap *dap, unsigned reg,
@@ -431,7 +430,7 @@ const struct dap_ops jtag_dp_ops = {
 };
 
 
-const uint8_t swd2jtag_bitseq[] = {
+static const uint8_t swd2jtag_bitseq[] = {
        /* More than 50 TCK/SWCLK cycles with TMS/SWDIO high,
         * putting both JTAG and SWD logic into reset state.
         */