ARM: rename some generic routines

[openocd.git] / src / target / arm11.c

diff --git a/src/target/arm11.c b/src/target/arm11.c
index 20ad22d50235dba2f23e5a670b6d0e720ed87749..7b29f53e36f5ed48e2b620f27f6d3e32a49b49d8 100644 (file)
--- a/src/target/arm11.c
+++ b/src/target/arm11.c
@@ -34,6 +34,7 @@
 #include "target_type.h"
 #include "algorithm.h"
 #include "register.h"
+#include "arm_opcodes.h"
 
 
 #if 0
@@ -217,6 +218,19 @@ static int arm11_debug_entry(struct arm11_common *arm11)
 
        }
 
+       if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
+               uint32_t wfar;
+
+               /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
+               retval = arm11_run_instr_data_from_core_via_r0(arm11,
+                               ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
+                               &wfar);
+               if (retval != ERROR_OK)
+                       return retval;
+               arm_dpm_report_wfar(arm11->arm.dpm, wfar);
+       }
+
+
        retval = arm11_run_instr_data_finish(arm11);
        if (retval != ERROR_OK)
                return retval;
@@ -286,6 +300,8 @@ static int arm11_leave_debug_state(struct arm11_common *arm11, bool bpwp)
         */
        retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
 
+       retval = arm11_bpwp_flush(arm11);
+
        register_cache_invalidate(arm11->arm.core_cache);
 
        /* restore DSCR */
@@ -354,12 +370,17 @@ static int arm11_poll(struct target *target)
 /* architecture specific status reply */
 static int arm11_arch_state(struct target *target)
 {
+       struct arm11_common *arm11 = target_to_arm11(target);
        int retval;
 
-       retval = armv4_5_arch_state(target);
+       retval = arm_arch_state(target);
 
        /* REVISIT also display ARM11-specific MMU and cache status ... */
 
+       if (target->debug_reason == DBG_REASON_WATCHPOINT)
+               LOG_USER("Watchpoint triggered at PC %#08x",
+                               (unsigned) arm11->dpm.wp_pc);
+
        return retval;
 }
 
@@ -513,7 +534,8 @@ static int arm11_resume(struct target *target, int current,
                        brp_num++;
                }
 
-               arm11_sc7_set_vcr(arm11, arm11_vcr);
+               if (arm11_vcr)
+                       arm11_sc7_set_vcr(arm11, arm11_vcr);
        }
 
        arm11_leave_debug_state(arm11, handle_breakpoints);
@@ -1128,12 +1150,12 @@ static int arm11_target_create(struct target *target, Jim_Interp *interp)
        if (!arm11)
                return ERROR_FAIL;
 
-       armv4_5_init_arch_info(target, &arm11->arm);
+       arm_init_arch_info(target, &arm11->arm);
 
        arm11->jtag_info.tap = target->tap;
        arm11->jtag_info.scann_size = 5;
        arm11->jtag_info.scann_instr = ARM11_SCAN_N;
-       /* cur_scan_chain == 0 */
+       arm11->jtag_info.cur_scan_chain = ~0;   /* invalid/unknown */
        arm11->jtag_info.intest_instr = ARM11_INTEST;
 
        return ERROR_OK;
@@ -1211,7 +1233,6 @@ static int arm11_examine(struct target *target)
        }
 
        arm11->brp = ((didr >> 24) & 0x0F) + 1;
-       arm11->wrp = ((didr >> 28) & 0x0F) + 1;
 
        /** \todo TODO: reserve one brp slot if we allow breakpoints during step */
        arm11->free_brps = arm11->brp;
@@ -1366,7 +1387,7 @@ struct target_type arm11_target = {
        .deassert_reset =       arm11_deassert_reset,
        .soft_reset_halt =      arm11_soft_reset_halt,
 
-       .get_gdb_reg_list =     armv4_5_get_gdb_reg_list,
+       .get_gdb_reg_list =     arm_get_gdb_reg_list,
 
        .read_memory =          arm11_read_memory,
        .write_memory =         arm11_write_memory,