#include "breakpoints.h"
#include "arm11_dbgtap.h"
#include "arm_simulator.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#include "target_type.h"
#include "algorithm.h"
#include "register.h"
+#include "arm_opcodes.h"
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#endif
+
+/* FIXME none of these flags should be global to all ARM11 cores!
+ * Most of them shouldn't exist at all, once the code works...
+ */
static bool arm11_config_memwrite_burst = true;
static bool arm11_config_memwrite_error_fatal = true;
static uint32_t arm11_vcr = 0;
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
- if (!(arm11->dscr & ARM11_DSCR_MODE_SELECT))
+ if (!(arm11->dscr & DSCR_HALT_DBG_MODE))
{
LOG_DEBUG("Bringing target into debug mode");
- arm11->dscr |= ARM11_DSCR_MODE_SELECT; /* Halt debug-mode */
+ arm11->dscr |= DSCR_HALT_DBG_MODE;
arm11_write_DSCR(arm11, arm11->dscr);
/* add further reset initialization here */
arm11->simulate_reset_on_next_halt = true;
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
* arm11_debug_entry() never gets called. (WHY NOT?)
*/
arm11->arm.target->state = TARGET_HALTED;
- arm11->arm.target->debug_reason =
- arm11_get_DSCR_debug_reason(arm11->dscr);
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
}
else
{
int retval;
arm11->arm.target->state = TARGET_HALTED;
- arm11->arm.target->debug_reason =
- arm11_get_DSCR_debug_reason(arm11->dscr);
+ arm_dpm_report_dscr(arm11->arm.dpm, arm11->dscr);
/* REVISIT entire cache should already be invalid !!! */
register_cache_invalidate(arm11->arm.core_cache);
/* See e.g. ARM1136 TRM, "14.8.4 Entering Debug state" */
/* maybe save wDTR (pending DCC write to debug SW, e.g. libdcc) */
- arm11->is_wdtr_saved = !!(arm11->dscr & ARM11_DSCR_WDTR_FULL);
+ arm11->is_wdtr_saved = !!(arm11->dscr & DSCR_DTR_TX_FULL);
if (arm11->is_wdtr_saved)
{
arm11_add_debug_SCAN_N(arm11, 0x05, ARM11_TAP_DEFAULT);
}
- /* DSCR: set ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
+ /* DSCR: set the Execute ARM instruction enable bit.
*
* ARM1176 spec says this is needed only for wDTR/rDTR's "ITR mode",
- * but not to issue ITRs. ARM1136 seems to require this to issue
- * ITR's as well...
+ * but not to issue ITRs(?). The ARMv7 arch spec says it's required
+ * for executing instructions via ITR.
*/
-
- arm11_write_DSCR(arm11, ARM11_DSCR_EXECUTE_ARM_INSTRUCTION_ENABLE
- | arm11->dscr);
+ arm11_write_DSCR(arm11, DSCR_ITR_EN | arm11->dscr);
/* From the spec:
return retval;
/* maybe save rDTR (pending DCC read from debug SW, e.g. libdcc) */
- arm11->is_rdtr_saved = !!(arm11->dscr & ARM11_DSCR_RDTR_FULL);
+ arm11->is_rdtr_saved = !!(arm11->dscr & DSCR_DTR_RX_FULL);
if (arm11->is_rdtr_saved)
{
/* MRC p14,0,R0,c0,c5,0 (move rDTR -> r0 (-> wDTR -> local var)) */
}
+ if (arm11->arm.target->debug_reason == DBG_REASON_WATCHPOINT) {
+ uint32_t wfar;
+
+ /* MRC p15, 0, <Rd>, c6, c0, 1 ; Read WFAR */
+ retval = arm11_run_instr_data_from_core_via_r0(arm11,
+ ARMV4_5_MRC(15, 0, 0, 6, 0, 1),
+ &wfar);
+ if (retval != ERROR_OK)
+ return retval;
+ arm_dpm_report_wfar(arm11->arm.dpm, wfar);
+ }
+
+
retval = arm11_run_instr_data_finish(arm11);
if (retval != ERROR_OK)
return retval;
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
- if (arm11->dscr & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
+ if (arm11->dscr & (DSCR_DTR_RX_FULL | DSCR_DTR_TX_FULL))
{
/*
The wDTR/rDTR two registers that are used to send/receive data to/from
*/
retval = arm_dpm_write_dirty_registers(&arm11->dpm, bpwp);
+ retval = arm11_bpwp_flush(arm11);
+
register_cache_invalidate(arm11->arm.core_cache);
/* restore DSCR */
CHECK_RETVAL(arm11_check_init(arm11));
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
{
if (target->state != TARGET_HALTED)
{
/* architecture specific status reply */
static int arm11_arch_state(struct target *target)
{
+ struct arm11_common *arm11 = target_to_arm11(target);
int retval;
- retval = armv4_5_arch_state(target);
+ retval = arm_arch_state(target);
/* REVISIT also display ARM11-specific MMU and cache status ... */
+ if (target->debug_reason == DBG_REASON_WATCHPOINT)
+ LOG_USER("Watchpoint triggered at PC %#08x",
+ (unsigned) arm11->dpm.wp_pc);
+
return retval;
}
{
CHECK_RETVAL(arm11_read_DSCR(arm11));
- if (arm11->dscr & ARM11_DSCR_CORE_HALTED)
+ if (arm11->dscr & DSCR_CORE_HALTED)
break;
brp_num++;
}
- arm11_sc7_set_vcr(arm11, arm11_vcr);
+ if (arm11_vcr)
+ arm11_sc7_set_vcr(arm11, arm11_vcr);
}
arm11_leave_debug_state(arm11, handle_breakpoints);
LOG_DEBUG("DSCR %08x", (unsigned) arm11->dscr);
- if (arm11->dscr & ARM11_DSCR_CORE_RESTARTED)
+ if (arm11->dscr & DSCR_CORE_RESTARTED)
break;
i++;
}
+ target->debug_reason = DBG_REASON_NOTHALTED;
if (!debug_execution)
- {
- target->state = TARGET_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
-
- CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
- }
+ target->state = TARGET_RUNNING;
else
- {
- target->state = TARGET_DEBUG_RUNNING;
- target->debug_reason = DBG_REASON_NOTHALTED;
-
- CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
- }
+ target->state = TARGET_DEBUG_RUNNING;
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
return ERROR_OK;
}
if (arm11_config_step_irq_enable)
/* this disable should be redundant ... */
- arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr &= ~DSCR_INT_DIS;
else
- arm11->dscr |= ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr |= DSCR_INT_DIS;
CHECK_RETVAL(arm11_leave_debug_state(arm11, handle_breakpoints));
while (1)
{
- const uint32_t mask = ARM11_DSCR_CORE_RESTARTED
- | ARM11_DSCR_CORE_HALTED;
+ const uint32_t mask = DSCR_CORE_RESTARTED
+ | DSCR_CORE_HALTED;
CHECK_RETVAL(arm11_read_DSCR(arm11));
LOG_DEBUG("DSCR %08x e", (unsigned) arm11->dscr);
CHECK_RETVAL(arm11_debug_entry(arm11));
/* restore default state */
- arm11->dscr &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
+ arm11->dscr &= ~DSCR_INT_DIS;
}
- target->debug_reason = DBG_REASON_SINGLESTEP;
+ target->debug_reason = DBG_REASON_SINGLESTEP;
CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
if (!arm11)
return ERROR_FAIL;
- armv4_5_init_arch_info(target, &arm11->arm);
+ arm_init_arch_info(target, &arm11->arm);
arm11->jtag_info.tap = target->tap;
arm11->jtag_info.scann_size = 5;
arm11->jtag_info.scann_instr = ARM11_SCAN_N;
- /* cur_scan_chain == 0 */
+ arm11->jtag_info.cur_scan_chain = ~0; /* invalid/unknown */
arm11->jtag_info.intest_instr = ARM11_INTEST;
return ERROR_OK;
}
arm11->brp = ((didr >> 24) & 0x0F) + 1;
- arm11->wrp = ((didr >> 28) & 0x0F) + 1;
/** \todo TODO: reserve one brp slot if we allow breakpoints during step */
arm11->free_brps = arm11->brp;
.deassert_reset = arm11_deassert_reset,
.soft_reset_halt = arm11_soft_reset_halt,
- .get_gdb_reg_list = armv4_5_get_gdb_reg_list,
+ .get_gdb_reg_list = arm_get_gdb_reg_list,
.read_memory = arm11_read_memory,
.write_memory = arm11_write_memory,