/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
+ * Michael Bruck *
* *
* Copyright (C) 2008 Oyvind Harboe oyvind.harboe@zylin.com *
* *
#endif
#include "arm11.h"
-#include "jtag.h"
-#include "log.h"
+#include "target_type.h"
-#include <stdlib.h>
-#include <string.h>
#if 0
#define _DEBUG_INSTRUCTION_EXECUTION_
#define FNC_INFO_NOTIMPLEMENTED
#endif
-static void arm11_on_enter_debug_state(arm11_common_t * arm11);
+static int arm11_on_enter_debug_state(arm11_common_t * arm11);
bool arm11_config_memwrite_burst = true;
bool arm11_config_memwrite_error_fatal = true;
* available a pointer to a word holding the
* DSCR can be passed. Otherwise use NULL.
*/
-void arm11_check_init(arm11_common_t * arm11, u32 * dscr)
+int arm11_check_init(arm11_common_t * arm11, u32 * dscr)
{
FNC_INFO;
if (!dscr)
{
dscr = &dscr_local_tmp_copy;
- *dscr = arm11_read_DSCR(arm11);
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, dscr));
}
if (!(*dscr & ARM11_DSCR_MODE_SELECT))
if (*dscr & ARM11_DSCR_CORE_HALTED)
{
/** \todo TODO: this needs further scrutiny because
- * arm11_on_enter_debug_state() never gets properly called
+ * arm11_on_enter_debug_state() never gets properly called.
+ * As a result we don't read the actual register states from
+ * the target.
*/
arm11->target->state = TARGET_HALTED;
arm11_sc7_clear_vbw(arm11);
}
+
+ return ERROR_OK;
}
* or on other occasions that stop the processor.
*
*/
-static void arm11_on_enter_debug_state(arm11_common_t * arm11)
+static int arm11_on_enter_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
- {size_t i;
- for(i = 0; i < asizeof(arm11->reg_values); i++)
+ for (size_t i = 0; i < asizeof(arm11->reg_values); i++)
{
arm11->reg_list[i].valid = 1;
arm11->reg_list[i].dirty = 0;
- }}
+ }
/* Save DSCR */
-
- R(DSCR) = arm11_read_DSCR(arm11);
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &R(DSCR)));
/* Save wDTR */
scan_field_t chain5_fields[3];
arm11_setup_field(arm11, 32, NULL, &R(WDTR), chain5_fields + 0);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
- arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 1);
+ arm11_setup_field(arm11, 1, NULL, NULL, chain5_fields + 2);
arm11_add_dr_scan_vc(asizeof(chain5_fields), chain5_fields, TAP_DRPAUSE);
}
/** \todo TODO: handle other mode registers */
- {size_t i;
- for (i = 0; i < 15; i++)
+ for (size_t i = 0; i < 15; i++)
{
/* MCR p14,0,R?,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE000E15 | (i << 12), &R(RX + i), 1);
- }}
+ }
/* save rDTR */
arm11_run_instr_data_finish(arm11);
arm11_dump_reg_changes(arm11);
+
+ return ERROR_OK;
}
void arm11_dump_reg_changes(arm11_common_t * arm11)
{
- {size_t i;
- for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
+
+ if (!(debug_level >= LOG_LVL_DEBUG))
+ {
+ return;
+ }
+
+ for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (!arm11->reg_list[i].valid)
{
if (arm11->reg_history[i].valid)
- LOG_INFO("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
+ LOG_DEBUG("%8s INVALID (%08x)", arm11_reg_defs[i].name, arm11->reg_history[i].value);
}
else
{
if (arm11->reg_history[i].valid)
{
if (arm11->reg_history[i].value != arm11->reg_values[i])
- LOG_INFO("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
+ LOG_DEBUG("%8s %08x (%08x)", arm11_reg_defs[i].name, arm11->reg_values[i], arm11->reg_history[i].value);
}
else
{
- LOG_INFO("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
+ LOG_DEBUG("%8s %08x (INVALID)", arm11_reg_defs[i].name, arm11->reg_values[i]);
}
}
- }}
+ }
}
/** Restore processor state
* This is called in preparation for the RESTART function.
*
*/
-void arm11_leave_debug_state(arm11_common_t * arm11)
+int arm11_leave_debug_state(arm11_common_t * arm11)
{
FNC_INFO;
/** \todo TODO: handle other mode registers */
/* restore R1 - R14 */
- {size_t i;
- for (i = 1; i < 15; i++)
+
+ for (size_t i = 1; i < 15; i++)
{
if (!arm11->reg_list[ARM11_RC_RX + i].dirty)
continue;
arm11_run_instr_data_to_core1(arm11, 0xee100e15 | (i << 12), R(RX + i));
// LOG_DEBUG("RESTORE R" ZU " %08x", i, R(RX + i));
- }}
+ }
arm11_run_instr_data_finish(arm11);
/* spec says clear wDTR and rDTR; we assume they are clear as
otherwise our programming would be sloppy */
{
- u32 DSCR = arm11_read_DSCR(arm11);
+ u32 DSCR;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &DSCR));
if (DSCR & (ARM11_DSCR_RDTR_FULL | ARM11_DSCR_WDTR_FULL))
{
}
arm11_record_register_history(arm11);
+
+ return ERROR_OK;
}
void arm11_record_register_history(arm11_common_t * arm11)
{
- {size_t i;
- for(i = 0; i < ARM11_REGCACHE_COUNT; i++)
+ for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
arm11->reg_history[i].value = arm11->reg_values[i];
arm11->reg_history[i].valid = arm11->reg_list[i].valid;
arm11->reg_list[i].valid = 0;
arm11->reg_list[i].dirty = 0;
- }}
+ }
}
if (arm11->trst_active)
return ERROR_OK;
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
- arm11_check_init(arm11, &dscr);
+ CHECK_RETVAL(arm11_check_init(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
{
enum target_state old_state = target->state;
LOG_DEBUG("enter TARGET_HALTED");
- target->state = TARGET_HALTED;
+ target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
arm11_on_enter_debug_state(arm11);
if (target->state != TARGET_RUNNING && target->state != TARGET_DEBUG_RUNNING)
{
LOG_DEBUG("enter TARGET_RUNNING");
- target->state = TARGET_RUNNING;
+ target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
}
}
/* architecture specific status reply */
int arm11_arch_state(struct target_s *target)
{
- FNC_INFO_NOTIMPLEMENTED;
+ arm11_common_t * arm11 = target->arch_info;
+
+ LOG_USER("target halted due to %s\ncpsr: 0x%8.8x pc: 0x%8.8x",
+ Jim_Nvp_value2name_simple( nvp_target_debug_reason, target->debug_reason )->name,
+ R(CPSR),
+ R(PC));
return ERROR_OK;
}
/* target execution control */
int arm11_halt(struct target_s *target)
{
- int retval = ERROR_OK;
-
FNC_INFO;
arm11_common_t * arm11 = target->arch_info;
arm11_add_IR(arm11, ARM11_HALT, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
u32 dscr;
while (1)
{
- dscr = arm11_read_DSCR(arm11);
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
if (dscr & ARM11_DSCR_CORE_HALTED)
break;
target->state = TARGET_HALTED;
target->debug_reason = arm11_get_DSCR_debug_reason(dscr);
- if((retval = target_call_event_callbacks(target,
- old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(
+ target_call_event_callbacks(target,
+ old_state == TARGET_DEBUG_RUNNING ? TARGET_EVENT_DEBUG_HALTED : TARGET_EVENT_HALTED));
return ERROR_OK;
}
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution)
{
- int retval = ERROR_OK;
-
FNC_INFO;
-
+
// LOG_DEBUG("current %d address %08x handle_breakpoints %d debug_execution %d",
// current, address, handle_breakpoints, debug_execution);
if (!current)
R(PC) = address;
- LOG_INFO("RESUME PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("RESUME PC %08x%s", R(PC), !current ? "!" : "");
/* clear breakpoints/watchpoints and VCR*/
arm11_sc7_clear_vbw(arm11);
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
target->state = TARGET_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
else
{
target->state = TARGET_DEBUG_RUNNING;
target->debug_reason = DBG_REASON_NOTHALTED;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_RESUMED)) != ERROR_OK)
- {
- return retval;
- }
+
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_RESUMED));
}
return ERROR_OK;
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints)
{
- int retval = ERROR_OK;
-
FNC_INFO;
LOG_DEBUG("target->state: %s",
if (!current)
R(PC) = address;
- LOG_INFO("STEP PC %08x%s", R(PC), !current ? "!" : "");
+ LOG_DEBUG("STEP PC %08x%s", R(PC), !current ? "!" : "");
/** \todo TODO: Thumb not supported here */
u32 next_instruction;
- arm11_read_memory_word(arm11, R(PC), &next_instruction);
+ CHECK_RETVAL(arm11_read_memory_word(arm11, R(PC), &next_instruction));
/* skip over BKPT */
if ((next_instruction & 0xFFF00070) == 0xe1200070)
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping BKPT");
+ LOG_DEBUG("Skipping BKPT");
}
/* skip over Wait for interrupt / Standby */
/* mcr 15, 0, r?, cr7, cr0, {4} */
R(PC) += 4;
arm11->reg_list[ARM11_RC_PC].valid = 1;
arm11->reg_list[ARM11_RC_PC].dirty = 0;
- LOG_INFO("Skipping WFI");
+ LOG_DEBUG("Skipping WFI");
}
/* ignore B to self */
else if ((next_instruction & 0xFEFFFFFF) == 0xeafffffe)
{
- LOG_INFO("Not stepping jump to self");
+ LOG_DEBUG("Not stepping jump to self");
}
else
{
brp[1].address = ARM11_SC7_BCR0;
brp[1].value = 0x1 | (3 << 1) | (0x0F << 5) | (0 << 14) | (0 << 16) | (0 << 20) | (2 << 21);
- arm11_sc7_run(arm11, brp, asizeof(brp));
+ CHECK_RETVAL(arm11_sc7_run(arm11, brp, asizeof(brp)));
/* resume */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE; /* should be redundant */
else
R(DSCR) |= ARM11_DSCR_INTERRUPTS_DISABLE;
-
- arm11_leave_debug_state(arm11);
+
+ CHECK_RETVAL(arm11_leave_debug_state(arm11));
arm11_add_IR(arm11, ARM11_RESTART, TAP_IDLE);
- if((retval = jtag_execute_queue()) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(jtag_execute_queue());
/** \todo TODO: add a timeout */
while (1)
{
- u32 dscr = arm11_read_DSCR(arm11);
+ u32 dscr;
+
+ CHECK_RETVAL(arm11_read_DSCR(arm11, &dscr));
LOG_DEBUG("DSCR %08x", dscr);
arm11_sc7_clear_vbw(arm11);
/* save state */
- arm11_on_enter_debug_state(arm11);
+ CHECK_RETVAL(arm11_on_enter_debug_state(arm11));
/* restore default state */
R(DSCR) &= ~ARM11_DSCR_INTERRUPTS_DISABLE;
// target->state = TARGET_HALTED;
target->debug_reason = DBG_REASON_SINGLESTEP;
- if((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_call_event_callbacks(target, TARGET_EVENT_HALTED));
return ERROR_OK;
}
if (target->reset_halt)
{
- int retval;
- if ((retval = target_halt(target))!=ERROR_OK)
- return retval;
+ CHECK_RETVAL(target_halt(target));
}
return ERROR_OK;
*reg_list_size = ARM11_GDB_REGISTER_COUNT;
*reg_list = malloc(sizeof(reg_t*) * ARM11_GDB_REGISTER_COUNT);
- {size_t i;
- for (i = 16; i < 24; i++)
+ for (size_t i = 16; i < 24; i++)
{
(*reg_list)[i] = &arm11_gdb_dummy_fp_reg;
- }}
+ }
(*reg_list)[24] = &arm11_gdb_dummy_fps_reg;
- {size_t i;
- for (i = 0; i < ARM11_REGCACHE_COUNT; i++)
+ for (size_t i = 0; i < ARM11_REGCACHE_COUNT; i++)
{
if (arm11_reg_defs[i].gdb_num == -1)
continue;
(*reg_list)[arm11_reg_defs[i].gdb_num] = arm11->reg_list + i;
- }}
+ }
return ERROR_OK;
}
/** \todo TODO: check if dirty is the right choice to force a rewrite on arm11_resume() */
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
/* ldrb r1, [r0], #1 */
/* ldrb r1, [r0] */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
*buffer++ = res;
- }}
+ }
break;
{
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- u16 * buf16 = (u16*)buffer;
-
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
/* ldrh r1, [r0], #2 */
arm11_run_instr_no_data1(arm11,
/* MCR p14,0,R1,c0,c5,0 */
arm11_run_instr_data_from_core(arm11, 0xEE001E15, &res, 1);
- *buf16++ = res;
- }}
+ u16 svalue = res;
+ memcpy(buffer + count * sizeof(u16), &svalue, sizeof(u16));
+ }
break;
}
case 4:
+ {
+ u32 instr = !arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00;
+ /** \todo TODO: buffer cast to u32* causes alignment warnings */
+ u32 *words = (u32 *)buffer;
/* LDC p14,c5,[R0],#4 */
/* LDC p14,c5,[R0] */
- arm11_run_instr_data_from_core(arm11,
- (!arm11_config_memrw_no_increment ? 0xecb05e01 : 0xed905e00),
- (u32 *)buffer, count);
+ arm11_run_instr_data_from_core(arm11, instr, words, count);
break;
+ }
}
arm11_run_instr_data_finish(arm11);
{
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
/* MRC p14,0,r1,c0,c5,0 */
arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buffer++);
/* strb r1, [r0] */
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe4c01001 : 0xe5c01000);
- }}
+ }
break;
}
{
arm11->reg_list[ARM11_RC_R1].dirty = 1;
- u16 * buf16 = (u16*)buffer;
-
- {size_t i;
- for (i = 0; i < count; i++)
+ for (size_t i = 0; i < count; i++)
{
+ u16 value;
+ memcpy(&value, buffer + count * sizeof(u16), sizeof(u16));
+
/* MRC p14,0,r1,c0,c5,0 */
- arm11_run_instr_data_to_core1(arm11, 0xee101e15, *buf16++);
+ arm11_run_instr_data_to_core1(arm11, 0xee101e15, value);
/* strh r1, [r0], #2 */
/* strh r1, [r0] */
arm11_run_instr_no_data1(arm11,
!arm11_config_memrw_no_increment ? 0xe0c010b2 : 0xe1c010b0);
- }}
+ }
break;
}
- case 4:
- /** \todo TODO: check if buffer cast to u32* might cause alignment problems */
+ case 4: {
+ u32 instr = !arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00;
+
+ /** \todo TODO: buffer cast to u32* causes alignment warnings */
+ u32 *words = (u32*)buffer;
if (!arm11_config_memwrite_burst)
{
/* STC p14,c5,[R0],#4 */
/* STC p14,c5,[R0]*/
- arm11_run_instr_data_to_core(arm11,
- (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
- (u32 *)buffer, count);
+ arm11_run_instr_data_to_core(arm11, instr, words, count);
}
else
{
/* STC p14,c5,[R0],#4 */
/* STC p14,c5,[R0]*/
- arm11_run_instr_data_to_core_noack(arm11,
- (!arm11_config_memrw_no_increment ? 0xeca05e01 : 0xed805e00),
- (u32 *)buffer, count);
+ arm11_run_instr_data_to_core_noack(arm11, instr, words, count);
}
break;
}
+ }
#if 1
/* r0 verification */
return arm11_write_memory(target, address, 4, count, buffer);
}
+/* here we have nothing target specific to contribute, so we fail and then the
+ * fallback code will read data from the target and calculate the CRC on the
+ * host.
+ */
int arm11_checksum_memory(struct target_s *target, u32 address, u32 count, u32* checksum)
{
- FNC_INFO_NOTIMPLEMENTED;
-
- return ERROR_OK;
+ return ERROR_FAIL;
}
/* target break-/watchpoint control
if (!arm11->free_brps)
{
- LOG_INFO("no breakpoint unit available for hardware breakpoint");
+ LOG_DEBUG("no breakpoint unit available for hardware breakpoint");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
if (breakpoint->length != 4)
{
- LOG_INFO("only breakpoints of four bytes length supported");
+ LOG_DEBUG("only breakpoints of four bytes length supported");
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
int timeout_ms, void *arch_info)
{
arm11_common_t *arm11 = target->arch_info;
- armv4_5_algorithm_t *arm11_algorithm_info = arch_info;
// enum armv4_5_state core_state = arm11->core_state;
// enum armv4_5_mode core_mode = arm11->core_mode;
u32 context[16];
u32 cpsr;
int exit_breakpoint_size = 0;
- int i;
int retval = ERROR_OK;
LOG_DEBUG("Running algorithm");
- if (arm11_algorithm_info->common_magic != ARMV4_5_COMMON_MAGIC)
- {
- LOG_ERROR("current target isn't an ARMV4/5 target");
- return ERROR_TARGET_INVALID;
- }
if (target->state != TARGET_HALTED)
{
// return ERROR_FAIL;
// Save regs
- for (i = 0; i < 16; i++)
+ for (size_t i = 0; i < 16; i++)
{
context[i] = buf_get_u32((u8*)(&arm11->reg_values[i]),0,32);
- LOG_DEBUG("Save %i: 0x%x",i,context[i]);
+ LOG_DEBUG("Save %zi: 0x%x",i,context[i]);
}
cpsr = buf_get_u32((u8*)(arm11->reg_values+ARM11_RC_CPSR),0,32);
LOG_DEBUG("Save CPSR: 0x%x", cpsr);
- for (i = 0; i < num_mem_params; i++)
+ for (int i = 0; i < num_mem_params; i++)
{
target_write_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
}
// Set register parameters
- for (i = 0; i < num_reg_params; i++)
+ for (int i = 0; i < num_reg_params; i++)
{
reg_t *reg = register_get_by_name(arm11->core_cache, reg_params[i].reg_name, 0);
if (!reg)
exit(-1);
}
*/
+
+
+/* arm11 at this point only supports ARM not THUMB mode
+ however if this test needs to be reactivated the current state can be read back
+ from CPSR */
+#if 0
if (arm11_algorithm_info->core_mode != ARMV4_5_MODE_ANY)
{
LOG_DEBUG("setting core_mode: 0x%2.2x", arm11_algorithm_info->core_mode);
arm11->reg_list[ARM11_RC_CPSR].dirty = 1;
arm11->reg_list[ARM11_RC_CPSR].valid = 1;
}
+#endif
if ((retval = breakpoint_add(target, exit_point, exit_breakpoint_size, BKPT_HARD)) != ERROR_OK)
{
}
// no debug, otherwise breakpoint is not set
- if((retval = target_resume(target, 0, entry_point, 1, 0)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_resume(target, 0, entry_point, 1, 0));
- if((retval = target_wait_state(target, TARGET_HALTED, timeout_ms)) != ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, timeout_ms));
if (target->state != TARGET_HALTED)
{
- if ((retval=target_halt(target))!=ERROR_OK)
- return retval;
- if ((retval=target_wait_state(target, TARGET_HALTED, 500))!=ERROR_OK)
- {
- return retval;
- }
+ CHECK_RETVAL(target_halt(target));
+
+ CHECK_RETVAL(target_wait_state(target, TARGET_HALTED, 500));
+
retval = ERROR_TARGET_TIMEOUT;
+
goto del_breakpoint;
}
goto del_breakpoint;
}
- for (i = 0; i < num_mem_params; i++)
+ for (int i = 0; i < num_mem_params; i++)
{
if (mem_params[i].direction != PARAM_OUT)
target_read_buffer(target, mem_params[i].address, mem_params[i].size, mem_params[i].value);
}
- for (i = 0; i < num_reg_params; i++)
+ for (int i = 0; i < num_reg_params; i++)
{
if (reg_params[i].direction != PARAM_OUT)
{
restore:
// Restore context
- for (i = 0; i < 16; i++)
+ for (size_t i = 0; i < 16; i++)
{
LOG_DEBUG("restoring register %s with value 0x%8.8x",
arm11->reg_list[i].name, context[i]);
int arm11_target_create(struct target_s *target, Jim_Interp *interp)
{
- int retval = ERROR_OK;
FNC_INFO;
NEW(arm11_common_t, arm11, 1);
arm11->target = target;
- /* prepare JTAG information for the new target */
- arm11->jtag_info.tap = target->tap;
- arm11->jtag_info.scann_size = 5;
-
- if((retval = arm_jtag_setup_connection(&arm11->jtag_info)) != ERROR_OK)
- {
- return retval;
- }
-
if (target->tap==NULL)
return ERROR_FAIL;
int arm11_examine(struct target_s *target)
{
FNC_INFO;
- int retval;
arm11_common_t * arm11 = target->arch_info;
arm11_add_dr_scan_vc(asizeof(chain0_fields), chain0_fields, TAP_IDLE);
- if ((retval=jtag_execute_queue())!=ERROR_OK)
- return retval;
-
+ CHECK_RETVAL(jtag_execute_queue());
switch (arm11->device_id & 0x0FFFF000)
{
arm11_check_init(arm11, NULL);
- target->type->examined = 1;
+ target_set_examined(target);
return ERROR_OK;
}
continue;
/* if (t->type == arm11_target) */
- if (0 == strcmp(t->type->name, "arm11"))
+ if (0 == strcmp(target_get_name(t), "arm11"))
return t->arch_info;
}
u32 values[6];
- {size_t i;
- for (i = 0; i < (read ? 5 : 6); i++)
+ for (size_t i = 0; i < (read ? 5 : 6); i++)
{
values[i] = strtoul(args[i + 1], NULL, 0);
read ? arm11_mrc_syntax : arm11_mcr_syntax);
return -1;
}
- }}
+ }
u32 instr = 0xEE000010 |
(values[0] << 8) |
RC_FINAL_BOOL( "error_fatal", "Terminate program if transfer error was found (default: enabled)",
memwrite_error_fatal)
- )
+ ) /* memwrite */
RC_FINAL_BOOL( "no_increment", "Don't increment address on multi-read/-write (default: disabled)",
memrw_no_increment)
-
+
RC_FINAL_BOOL( "step_irq_enable", "Enable interrupts while stepping (default: disabled)",
step_irq_enable)
RC_FINAL( "mcr", "Write Coprocessor register",
arm11_handle_mcr)
- )
+ ) /* arm11 */
return ERROR_OK;
}
Code Review / openocd.git / blobdiff