/***************************************************************************
* Copyright (C) 2008 digenius technology GmbH. *
* *
+ * Copyright (C) 2008 Georg Acher <acher@in.tum.de> *
+ * *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
+
#ifndef ARM11_H
#define ARM11_H
#include "register.h"
#include "embeddedice.h"
#include "arm_jtag.h"
+#include <stdbool.h>
#define asizeof(x) (sizeof(x) / sizeof((x)[0]))
-#define NEW(type, variable, items) \
- type * variable = malloc(sizeof(type) * items)
+#define NEW(type, variable, items) \
+ type * variable = calloc(1, sizeof(type) * items)
+
+
+/* For MinGW use 'I' prefix to print size_t (instead of 'z') */
+
+#ifndef __MSVCRT__
+#define ZU "%zu"
+#else
+#define ZU "%Iu"
+#endif
#define ARM11_REGCACHE_MODEREGS 0
u32 last_dscr; /**< Last retrieved DSCR value;
* Can be used to detect changes */
- u8 trst_active;
- u8 halt_requested;
+ bool trst_active;
+ bool halt_requested;
+ bool simulate_reset_on_next_halt;
/** \name Shadow registers to save processor state */
/*@{*/
size_t free_brps; /**< keep track of breakpoints allocated by arm11_add_breakpoint() */
size_t free_wrps; /**< keep track of breakpoints allocated by arm11_add_watchpoint() */
+ // GA
+ reg_cache_t *core_cache;
} arm11_common_t;
int arm11_halt(struct target_s *target);
int arm11_resume(struct target_s *target, int current, u32 address, int handle_breakpoints, int debug_execution);
int arm11_step(struct target_s *target, int current, u32 address, int handle_breakpoints);
+int arm11_examine(struct target_s *target);
/* target reset control */
int arm11_assert_reset(struct target_s *target);
int arm11_deassert_reset(struct target_s *target);
int arm11_soft_reset_halt(struct target_s *target);
-int arm11_prepare_reset_halt(struct target_s *target);
/* target register access for gdb */
int arm11_get_gdb_reg_list(struct target_s *target, struct reg_s **reg_list[], int *reg_list_size);
int arm11_run_algorithm(struct target_s *target, int num_mem_params, mem_param_t *mem_params, int num_reg_params, reg_param_t *reg_param, u32 entry_point, u32 exit_point, int timeout_ms, void *arch_info);
int arm11_register_commands(struct command_context_s *cmd_ctx);
-int arm11_target_command(struct command_context_s *cmd_ctx, char *cmd, char **args, int argc, struct target_s *target);
+int arm11_target_create(struct target_s *target, Jim_Interp *interp);
int arm11_init_target(struct command_context_s *cmd_ctx, struct target_s *target);
int arm11_quit(void);
*/
typedef struct arm11_sc7_action_s
{
- int write; /**< Access mode: true for write, false for read. */
+ bool write; /**< Access mode: true for write, false for read. */
u8 address; /**< Register address mode. Use enum #arm11_sc7 */
u32 value; /**< If write then set this to value to be written.
In read mode this receives the read value when the