#include "config.h"
#endif
-#include "arm11.h"
+#include "arm11_dbgtap.h"
#include "time_support.h"
Conversely there may be other places in this code where the ARM11 code relies
on the driver to hit through RTI when coming from Update-?R.
*/
-tap_state_t arm11_move_pi_to_si_via_ci[] =
+static const tap_state_t arm11_move_pi_to_si_via_ci[] =
{
TAP_IREXIT2, TAP_IRUPDATE, TAP_DRSELECT, TAP_IRSELECT, TAP_IRCAPTURE, TAP_IRSHIFT
};
return ERROR_OK;
}
-tap_state_t arm11_move_pd_to_sd_via_cd[] =
+static const tap_state_t arm11_move_pd_to_sd_via_cd[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
* https://lists.berlios.de/pipermail/openocd-development/2009-July/009698.html
* https://lists.berlios.de/pipermail/openocd-development/2009-August/009865.html
*/
-tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
+static const tap_state_t arm11_MOVE_DRPAUSE_IDLE_DRPAUSE_with_delay[] =
{
TAP_DREXIT2, TAP_DRUPDATE, TAP_IDLE, TAP_IDLE, TAP_IDLE, TAP_DRSELECT, TAP_DRCAPTURE, TAP_DRSHIFT
};
}
+/** Write Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Value to be written
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_write_etm(arm11_common_t * arm11, uint8_t address, uint32_t value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 1;
+
+ arm11_setup_field(arm11, 32, &value, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ return ERROR_OK;
+}
+
+/** Read Embedded Trace Macrocell (ETM) via Scan chain 6
+ *
+ * http://infocenter.arm.com/help/topic/com.arm.doc.ddi0318e/Bcfddjeh.html#Bcfggcbe
+ *
+ * \param arm11 Target state variable.
+ * \param address 7 bit ETM register address
+ * \param value Pointer that receives value that was read
+ *
+ * \return Error status
+ *
+ * \remarks This is a stand-alone function that executes the JTAG command queue.
+ */
+int arm11_read_etm(arm11_common_t * arm11, uint8_t address, uint32_t * value)
+{
+ CHECK_RETVAL(arm11_add_debug_SCAN_N(arm11, 0x06, ARM11_TAP_DEFAULT));
+
+ /* Uses INTEST for read and write */
+ arm11_add_IR(arm11, ARM11_INTEST, ARM11_TAP_DEFAULT);
+
+ scan_field_t chain6_fields[3];
+
+ uint8_t nRW = 0;
+
+ arm11_setup_field(arm11, 32, NULL, NULL, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ /* Data is made available in Capture-DR and shifted out on the next access */
+
+ arm11_setup_field(arm11, 32, NULL, value, chain6_fields + 0);
+ arm11_setup_field(arm11, 7, &address, NULL, chain6_fields + 1);
+ arm11_setup_field(arm11, 1, &nRW, NULL, chain6_fields + 2);
+
+ arm11_add_dr_scan_vc(asizeof(chain6_fields), chain6_fields, TAP_IDLE);
+
+ CHECK_RETVAL(jtag_execute_queue());
+
+ return ERROR_OK;
+}
+