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ARM11: use shared DSCR bit names
[openocd.git] / src / target / arm7_9_common.c
diff --git a/src/target/arm7_9_common.c b/src/target/arm7_9_common.c
index a58bd3bd6357896e538612fb3330ed7f9e8cd289..255a85f57f8207e3406e3cf68d3eb4549af71531 100644 (file)
--- a/src/target/arm7_9_common.c
+++ b/src/target/arm7_9_common.c
@@ -34,7 +34,7 @@
 #include "embeddedice.h"
 #include "target_request.h"
 #include "etm.h"
-#include "time_support.h"
+#include <helper/time_support.h>
 #include "arm_simulator.h"
 #include "algorithm.h"
 #include "register.h"
@@ -426,12 +426,6 @@ int arm7_9_add_breakpoint(struct target *target, struct breakpoint *breakpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (target->state != TARGET_HALTED)
-       {
-               LOG_WARNING("target not halted");
-               return ERROR_TARGET_NOT_HALTED;
-       }
-
        if (arm7_9->breakpoint_count == 0)
        {
                /* make sure we don't have any dangling breakpoints. This is vital upon
@@ -631,12 +625,6 @@ int arm7_9_add_watchpoint(struct target *target, struct watchpoint *watchpoint)
 {
        struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
 
-       if (target->state != TARGET_HALTED)
-       {
-               LOG_WARNING("target not halted");
-               return ERROR_TARGET_NOT_HALTED;
-       }
-
        if (arm7_9->wp_available < 1)
        {
                return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
@@ -1245,9 +1233,11 @@ int arm7_9_soft_reset_halt(struct target *target)
        /* reset registers */
        for (i = 0; i <= 14; i++)
        {
-               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, 0xffffffff);
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 1;
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
+               struct reg *r = arm_reg_current(armv4_5, i);
+
+               buf_set_u32(r->value, 0, 32, 0xffffffff);
+               r->dirty = 1;
+               r->valid = 1;
        }
 
        if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
@@ -1443,32 +1433,31 @@ static int arm7_9_debug_entry(struct target *target)
 
        for (i = 0; i <= 15; i++)
        {
+               struct reg *r = arm_reg_current(armv4_5, i);
+
                LOG_DEBUG("r%i: 0x%8.8" PRIx32 "", i, context[i]);
-               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).value, 0, 32, context[i]);
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = 0;
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid = 1;
+
+               buf_set_u32(r->value, 0, 32, context[i]);
+               /* r0 and r15 (pc) have to be restored later */
+               r->dirty = (i == 0) || (i == 15);
+               r->valid = 1;
        }
 
        LOG_DEBUG("entered debug state at PC 0x%" PRIx32 "", context[15]);
 
        /* exceptions other than USR & SYS have a saved program status register */
-       if ((armv4_5->core_mode != ARMV4_5_MODE_USR) && (armv4_5->core_mode != ARMV4_5_MODE_SYS))
-       {
+       if (armv4_5->spsr) {
                uint32_t spsr;
                arm7_9->read_xpsr(target, &spsr, 1);
                if ((retval = jtag_execute_queue()) != ERROR_OK)
                {
                        return retval;
                }
-               buf_set_u32(ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).value, 0, 32, spsr);
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).dirty = 0;
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 16).valid = 1;
+               buf_set_u32(armv4_5->spsr->value, 0, 32, spsr);
+               armv4_5->spsr->dirty = 0;
+               armv4_5->spsr->valid = 1;
        }
 
-       /* r0 and r15 (pc) have to be restored later */
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 0).valid;
-       ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, 15).valid;
-
        if ((retval = jtag_execute_queue()) != ERROR_OK)
                return retval;
 
@@ -2377,8 +2366,11 @@ int arm7_9_read_memory(struct target *target, uint32_t address, uint32_t size, u
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       for (i = 0; i <= last_reg; i++)
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
+       for (i = 0; i <= last_reg; i++) {
+               struct reg *r = arm_reg_current(armv4_5, i);
+
+               r->dirty = r->valid;
+       }
 
        arm7_9->read_xpsr(target, &cpsr, 0);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2562,8 +2554,11 @@ int arm7_9_write_memory(struct target *target, uint32_t address, uint32_t size,
        if (!is_arm_mode(armv4_5->core_mode))
                return ERROR_FAIL;
 
-       for (i = 0; i <= last_reg; i++)
-               ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).dirty = ARMV4_5_CORE_REG_MODE(armv4_5->core_cache, armv4_5->core_mode, i).valid;
+       for (i = 0; i <= last_reg; i++) {
+               struct reg *r = arm_reg_current(armv4_5, i);
+
+               r->dirty = r->valid;
+       }
 
        arm7_9->read_xpsr(target, &cpsr, 0);
        if ((retval = jtag_execute_queue()) != ERROR_OK)
@@ -2652,7 +2647,13 @@ static const uint32_t dcc_code[] =
        0xeafffff9      /*    b   w                   */
 };
 
-int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
+extern int armv4_5_run_algorithm_inner(struct target *target,
+       int num_mem_params, struct mem_param *mem_params,
+       int num_reg_params, struct reg_param *reg_params,
+       uint32_t entry_point, uint32_t exit_point,
+       int timeout_ms, void *arch_info,
+       int (*run_it)(struct target *target, uint32_t exit_point,
+                       int timeout_ms, void *arch_info));
 
 int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
 {
@@ -2702,7 +2703,9 @@ int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t c
        dcc_count = count;
        dcc_buffer = buffer;
        retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
-                       arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+                       arm7_9->dcc_working_area->address,
+                               arm7_9->dcc_working_area->address + 6*4,
+                       20*1000, &armv4_5_info, arm7_9_dcc_completion);
 
        if (retval == ERROR_OK)
        {
@@ -2840,28 +2843,44 @@ int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
                        1, 1, target);
 }
 
-int arm7_9_register_commands(struct command_context *cmd_ctx)
-{
-       struct command *arm7_9_cmd;
-
-       arm7_9_cmd = register_command(cmd_ctx, NULL, "arm7_9",
-                       NULL, COMMAND_ANY, "arm7/9 specific commands");
-
-       register_command(cmd_ctx, arm7_9_cmd, "dbgrq",
-                       handle_arm7_9_dbgrq_command, COMMAND_ANY,
-                       "use EmbeddedICE dbgrq instead of breakpoint "
-                       "for target halt requests <enable | disable>");
-       register_command(cmd_ctx, arm7_9_cmd, "fast_memory_access",
-                       handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
-                       "use fast memory accesses instead of slower "
-                       "but potentially safer accesses <enable | disable>");
-       register_command(cmd_ctx, arm7_9_cmd, "dcc_downloads",
-                       handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
-                       "use DCC downloads for larger memory writes <enable | disable>");
-
-       armv4_5_register_commands(cmd_ctx);
-
-       etm_register_commands(cmd_ctx);
-
-       return ERROR_OK;
-}
+static const struct command_registration arm7_9_any_command_handlers[] = {
+       {
+               "dbgrq",
+               .handler = &handle_arm7_9_dbgrq_command,
+               .mode = COMMAND_ANY,
+               .usage = "<enable|disable>",
+               .help = "use EmbeddedICE dbgrq instead of breakpoint "
+                       "for target halt requests",
+       },
+       {
+               "fast_memory_access",
+               .handler = &handle_arm7_9_fast_memory_access_command,
+               .mode = COMMAND_ANY,
+               .usage = "<enable|disable>",
+               .help = "use fast memory accesses instead of slower "
+                       "but potentially safer accesses",
+       },
+       {
+               "dcc_downloads",
+               .handler = &handle_arm7_9_dcc_downloads_command,
+               .mode = COMMAND_ANY,
+               .usage = "<enable | disable>",
+               .help = "use DCC downloads for larger memory writes",
+       },
+       COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm7_9_command_handlers[] = {
+       {
+               .chain = arm_command_handlers,
+       },
+       {
+               .chain = etm_command_handlers,
+       },
+       {
+               .name = "arm7_9",
+               .mode = COMMAND_ANY,
+               .help = "arm7/9 specific commands",
+               .chain = arm7_9_any_command_handlers,
+       },
+       COMMAND_REGISTRATION_DONE
+};
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