return jtag_execute_queue();
}
+static void arm7_9_assign_wp(arm7_9_common_t *arm7_9, breakpoint_t *breakpoint)
+{
+ if (!arm7_9->wp0_used)
+ {
+ arm7_9->wp0_used = 1;
+ breakpoint->set = 1;
+ arm7_9->wp_available--;
+ }
+ else if (!arm7_9->wp1_used)
+ {
+ arm7_9->wp1_used = 1;
+ breakpoint->set = 2;
+ arm7_9->wp_available--;
+ }
+ else
+ {
+ LOG_ERROR("BUG: no hardware comparator available");
+ }
+}
+
/* set up embedded ice registers */
static int arm7_9_set_software_breakpoints(arm7_9_common_t *arm7_9)
{
{
/* either an ARM (4 byte) or Thumb (2 byte) breakpoint */
u32 mask = (breakpoint->length == 4) ? 0x3u : 0x1u;
+
+ /* reassign a hw breakpoint */
+ if (breakpoint->set==0)
+ {
+ arm7_9_assign_wp(arm7_9, breakpoint);
+ }
+
if (breakpoint->set==1)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_ADDR_VALUE], breakpoint->address);
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W0_CONTROL_VALUE], 0x0);
arm7_9->wp0_used = 0;
+ arm7_9->wp_available++;
}
else if (breakpoint->set == 2)
{
embeddedice_set_reg(&arm7_9->eice_cache->reg_list[EICE_W1_CONTROL_VALUE], 0x0);
arm7_9->wp1_used = 0;
+ arm7_9->wp_available++;
}
retval = jtag_execute_queue();
breakpoint->set = 0;
if (breakpoint->type == BKPT_HARD)
{
- arm7_9->wp_available--;
-
- if (!arm7_9->wp0_used)
- {
- arm7_9->wp0_used = 1;
- breakpoint->set = 1;
- }
- else if (!arm7_9->wp1_used)
- {
- arm7_9->wp1_used = 1;
- breakpoint->set = 2;
- }
- else
- {
- LOG_ERROR("BUG: no hardware comparator available");
- }
+ arm7_9_assign_wp(arm7_9, breakpoint);
}
arm7_9->breakpoint_count++;
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
arm_jtag_t *jtag_info = &arm7_9->jtag_info;
u32 *data;
- int i, retval = ERROR_OK;
+ int retval = ERROR_OK;
+ u32 i;
data = malloc(size * (sizeof(u32)));
arm7_9_common_t *arm7_9 = armv4_5->arch_info;
u32 reg[16];
- int num_accesses = 0;
+ u32 num_accesses = 0;
int thisrun_accesses;
int i;
u32 cpsr;
reg_t *dbg_ctrl = &arm7_9->eice_cache->reg_list[EICE_DBG_CTRL];
u32 reg[16];
- int num_accesses = 0;
+ u32 num_accesses = 0;
int thisrun_accesses;
int i;
u32 cpsr;
0x04C11DB7 /* CRC32XOR: .word 0x04C11DB7 */
};
- int i;
+ u32 i;
if (target_alloc_working_area(target, sizeof(arm7_9_crc_code), &crc_algorithm) != ERROR_OK)
{
reg_param_t reg_params[3];
armv4_5_algorithm_t armv4_5_info;
int retval;
- int i;
+ u32 i;
u32 erase_check_code[] =
{