#include "embeddedice.h"
#include "target_request.h"
#include "etm.h"
-#include "time_support.h"
+#include <helper/time_support.h>
#include "arm_simulator.h"
+#include "arm_semihosting.h"
#include "algorithm.h"
#include "register.h"
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (arm7_9->breakpoint_count == 0)
{
/* make sure we don't have any dangling breakpoints. This is vital upon
{
struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
- if (target->state != TARGET_HALTED)
- {
- LOG_WARNING("target not halted");
- return ERROR_TARGET_NOT_HALTED;
- }
-
if (arm7_9->wp_available < 1)
{
return ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
}
}
+ if (arm_semihosting(target, &retval) != 0)
+ return retval;
+
if ((retval = target_call_event_callbacks(target, TARGET_EVENT_HALTED)) != ERROR_OK)
{
return retval;
0xeafffff9 /* b w */
};
-int armv4_5_run_algorithm_inner(struct target *target, int num_mem_params, struct mem_param *mem_params, int num_reg_params, struct reg_param *reg_params, uint32_t entry_point, uint32_t exit_point, int timeout_ms, void *arch_info, int (*run_it)(struct target *target, uint32_t exit_point, int timeout_ms, void *arch_info));
+extern int armv4_5_run_algorithm_inner(struct target *target,
+ int num_mem_params, struct mem_param *mem_params,
+ int num_reg_params, struct reg_param *reg_params,
+ uint32_t entry_point, uint32_t exit_point,
+ int timeout_ms, void *arch_info,
+ int (*run_it)(struct target *target, uint32_t exit_point,
+ int timeout_ms, void *arch_info));
int arm7_9_bulk_write_memory(struct target *target, uint32_t address, uint32_t count, uint8_t *buffer)
{
dcc_count = count;
dcc_buffer = buffer;
retval = armv4_5_run_algorithm_inner(target, 0, NULL, 1, reg_params,
- arm7_9->dcc_working_area->address, arm7_9->dcc_working_area->address + 6*4, 20*1000, &armv4_5_info, arm7_9_dcc_completion);
+ arm7_9->dcc_working_area->address,
+ arm7_9->dcc_working_area->address + 6*4,
+ 20*1000, &armv4_5_info, arm7_9_dcc_completion);
if (retval == ERROR_OK)
{
return ERROR_OK;
}
+COMMAND_HANDLER(handle_arm7_9_semihosting_command)
+{
+ struct target *target = get_current_target(CMD_CTX);
+ struct arm7_9_common *arm7_9 = target_to_arm7_9(target);
+
+ if (!is_arm7_9(arm7_9))
+ {
+ command_print(CMD_CTX, "current target isn't an ARM7/ARM9 target");
+ return ERROR_TARGET_INVALID;
+ }
+
+ if (CMD_ARGC > 0)
+ {
+ int semihosting;
+
+ COMMAND_PARSE_ENABLE(CMD_ARGV[0], semihosting);
+
+ /* TODO: support other methods if vector catch is unavailable */
+ if (arm7_9->has_vector_catch) {
+ struct reg *vector_catch = &arm7_9->eice_cache
+ ->reg_list[EICE_VEC_CATCH];
+
+ if (!vector_catch->valid)
+ embeddedice_read_reg(vector_catch);
+ buf_set_u32(vector_catch->value, 2, 1, semihosting);
+ embeddedice_store_reg(vector_catch);
+
+ /* FIXME never let that "catch" be dropped! */
+
+ arm7_9->armv4_5_common.is_semihosting = semihosting;
+
+ } else if (semihosting) {
+ command_print(CMD_CTX, "vector catch unavailable");
+ }
+ }
+
+ command_print(CMD_CTX, "semihosting is %s",
+ arm7_9->armv4_5_common.is_semihosting
+ ? "enabled" : "disabled");
+
+ return ERROR_OK;
+}
+
int arm7_9_init_arch_info(struct target *target, struct arm7_9_common *arm7_9)
{
int retval = ERROR_OK;
1, 1, target);
}
-int arm7_9_register_commands(struct command_context *cmd_ctx)
-{
- struct command *arm7_9_cmd;
-
- arm7_9_cmd = COMMAND_REGISTER(cmd_ctx, NULL, "arm7_9",
- NULL, COMMAND_ANY, "arm7/9 specific commands");
-
- COMMAND_REGISTER(cmd_ctx, arm7_9_cmd, "dbgrq",
- handle_arm7_9_dbgrq_command, COMMAND_ANY,
- "use EmbeddedICE dbgrq instead of breakpoint "
- "for target halt requests <enable | disable>");
- COMMAND_REGISTER(cmd_ctx, arm7_9_cmd, "fast_memory_access",
- handle_arm7_9_fast_memory_access_command, COMMAND_ANY,
- "use fast memory accesses instead of slower "
- "but potentially safer accesses <enable | disable>");
- COMMAND_REGISTER(cmd_ctx, arm7_9_cmd, "dcc_downloads",
- handle_arm7_9_dcc_downloads_command, COMMAND_ANY,
- "use DCC downloads for larger memory writes <enable | disable>");
-
- armv4_5_register_commands(cmd_ctx);
-
- etm_register_commands(cmd_ctx);
-
- return ERROR_OK;
-}
+static const struct command_registration arm7_9_any_command_handlers[] = {
+ {
+ "dbgrq",
+ .handler = &handle_arm7_9_dbgrq_command,
+ .mode = COMMAND_ANY,
+ .usage = "<enable|disable>",
+ .help = "use EmbeddedICE dbgrq instead of breakpoint "
+ "for target halt requests",
+ },
+ {
+ "fast_memory_access",
+ .handler = &handle_arm7_9_fast_memory_access_command,
+ .mode = COMMAND_ANY,
+ .usage = "<enable|disable>",
+ .help = "use fast memory accesses instead of slower "
+ "but potentially safer accesses",
+ },
+ {
+ "dcc_downloads",
+ .handler = &handle_arm7_9_dcc_downloads_command,
+ .mode = COMMAND_ANY,
+ .usage = "<enable | disable>",
+ .help = "use DCC downloads for larger memory writes",
+ },
+ {
+ "semihosting",
+ .handler = &handle_arm7_9_semihosting_command,
+ .mode = COMMAND_EXEC,
+ .usage = "<enable | disable>",
+ .help = "activate support for semihosting operations",
+ },
+ COMMAND_REGISTRATION_DONE
+};
+const struct command_registration arm7_9_command_handlers[] = {
+ {
+ .chain = arm_command_handlers,
+ },
+ {
+ .chain = etm_command_handlers,
+ },
+ {
+ .name = "arm7_9",
+ .mode = COMMAND_ANY,
+ .help = "arm7/9 specific commands",
+ .chain = arm7_9_any_command_handlers,
+ },
+ COMMAND_REGISTRATION_DONE
+};