- added patch by Øyvind Harboe to Intel Hex Start Segment Address Record (Type 3)

[openocd.git] / src / target / arm926ejs.c

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4d43c17a90c7005df2a7b42fe03e9e51d7b7c70e..ef225145cbbb8f6dc017f8d69c5dcc047dfed9ea 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -63,6 +63,8 @@ target_type_t arm926ejs_target =
        .poll = arm7_9_poll,
        .arch_state = arm926ejs_arch_state,
 
+       .target_request_data = arm7_9_target_request_data,
+
        .halt = arm7_9_halt,
        .resume = arm7_9_resume,
        .step = arm7_9_step,
@@ -77,7 +79,8 @@ target_type_t arm926ejs_target =
        .read_memory = arm7_9_read_memory,
        .write_memory = arm926ejs_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -477,7 +480,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        /* read-modify-write CP15 cache debug control register 
         * to reenable I/D-cache linefills and disable WT */
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
-       cache_dbg_ctrl |= 0x7;
+       cache_dbg_ctrl &= ~0x7;
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 }
 
@@ -566,7 +569,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();