fixed incorrect elf segment size - Thanks Øyvind Harboe

[openocd.git] / src / target / arm926ejs.c

diff --git a/src/target/arm926ejs.c b/src/target/arm926ejs.c
index 4d43c17a90c7005df2a7b42fe03e9e51d7b7c70e..efead81b8329b38aa6f6f046fc84fe72b27c7539 100644 (file)
--- a/src/target/arm926ejs.c
+++ b/src/target/arm926ejs.c
@@ -63,6 +63,8 @@ target_type_t arm926ejs_target =
        .poll = arm7_9_poll,
        .arch_state = arm926ejs_arch_state,
 
+       .target_request_data = arm7_9_target_request_data,
+
        .halt = arm7_9_halt,
        .resume = arm7_9_resume,
        .step = arm7_9_step,
@@ -77,7 +79,8 @@ target_type_t arm926ejs_target =
        .read_memory = arm7_9_read_memory,
        .write_memory = arm926ejs_write_memory,
        .bulk_write_memory = arm7_9_bulk_write_memory,
-
+       .checksum_memory = arm7_9_checksum_memory,
+       
        .run_algorithm = armv4_5_run_algorithm,
 
        .add_breakpoint = arm7_9_add_breakpoint,
@@ -91,12 +94,14 @@ target_type_t arm926ejs_target =
        .quit = arm926ejs_quit
 };
 
-int arm926ejs_catch_broken_irscan(u8 *in_value, void *priv)
+
+int arm926ejs_catch_broken_irscan(u8 *captured, void *priv, scan_field_t *field)
 {
-       /* The ARM926EJ-S' instruction register is 4 bits wide */
-       *in_value &= 0xf;
+       u8 *in_value=field->in_check_value;
        
-       if ((*in_value == 0x0f) || (*in_value == 0x00))
+       /* The ARM926EJ-S' instruction register is 4 bits wide */
+       u8 t=*in_value & 0xf;
+       if ((t == 0x0f) || (t == 0x00))
        {
                DEBUG("caught ARM926EJ-S invalid Capture-IR result after CP15 access");
                return ERROR_OK;
@@ -116,7 +121,6 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
        u8 address_buf[2];
        u8 nr_w_buf = 0;
        u8 access = 1;
-       error_handler_t error_handler;
        
        buf_set_u32(address_buf, 0, 14, address);
        
@@ -181,11 +185,8 @@ int arm926ejs_read_cp15(target_t *target, u32 address, u32 *value)
 #ifdef _DEBUG_INSTRUCTION_EXECUTION_
        DEBUG("addr: 0x%x value: %8.8x", address, *value);
 #endif
-
-       error_handler.error_handler = arm926ejs_catch_broken_irscan;
-       error_handler.error_handler_priv = NULL;
        
-       arm_jtag_set_instr(jtag_info, 0xc, &error_handler);
+       arm_jtag_set_instr(jtag_info, 0xc, &arm926ejs_catch_broken_irscan);
 
        return ERROR_OK;
 }
@@ -200,7 +201,6 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
        u8 address_buf[2];
        u8 nr_w_buf = 1;
        u8 access = 1;
-       error_handler_t error_handler;
        
        buf_set_u32(address_buf, 0, 14, address);
        buf_set_u32(value_buf, 0, 32, value);
@@ -264,10 +264,7 @@ int arm926ejs_write_cp15(target_t *target, u32 address, u32 value)
        DEBUG("addr: 0x%x value: %8.8x", address, value);
 #endif
 
-       error_handler.error_handler = arm926ejs_catch_broken_irscan;
-       error_handler.error_handler_priv = NULL;
-       
-       arm_jtag_set_instr(jtag_info, 0xf, &error_handler);
+       arm_jtag_set_instr(jtag_info, 0xf, &arm926ejs_catch_broken_irscan);
 
        return ERROR_OK;
 }
@@ -477,7 +474,7 @@ void arm926ejs_pre_restore_context(target_t *target)
        /* read-modify-write CP15 cache debug control register 
         * to reenable I/D-cache linefills and disable WT */
        arm926ejs_read_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), &cache_dbg_ctrl);
-       cache_dbg_ctrl |= 0x7;
+       cache_dbg_ctrl &= ~0x7;
        arm926ejs_write_cp15(target, ARM926EJS_CP15_ADDR(7, 0, 15, 0), cache_dbg_ctrl);
 }
 
@@ -566,7 +563,7 @@ int arm926ejs_soft_reset_halt(struct target_s *target)
                target->type->halt(target);
        }
        
-       while (buf_get_u32(dbg_stat->value, EICE_DBG_CONTROL_DBGACK, 1) == 0)
+       while (buf_get_u32(dbg_stat->value, EICE_DBG_STATUS_DBGACK, 1) == 0)
        {
                embeddedice_read_reg(dbg_stat);
                jtag_execute_queue();