.assert_reset = arm7_9_assert_reset,
.deassert_reset = arm7_9_deassert_reset,
.soft_reset_halt = arm7_9_soft_reset_halt,
+ .prepare_reset_halt = arm7_9_prepare_reset_halt,
.get_gdb_reg_list = armv4_5_get_gdb_reg_list,
{0, 0},
};
+int arm9tdmi_jtag_error_handler(u8 *in_value, void *priv)
+{
+ char *caller = priv;
+
+ DEBUG("caller: %s", caller);
+
+ return ERROR_OK;
+}
+
int arm9tdmi_examine_debug_reason(target_t *target)
{
/* get pointers to arch-specific information */
if ((target->debug_reason != DBG_REASON_DBGRQ)
&& (target->debug_reason != DBG_REASON_SINGLESTEP))
{
+ error_handler_t error_handler;
scan_field_t fields[3];
u8 databus[4];
u8 instructionbus[4];
fields[2].in_handler_priv = NULL;
arm_jtag_scann(&arm7_9->jtag_info, 0x1);
- arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr);
+ error_handler.error_handler = arm9tdmi_jtag_error_handler;
+ error_handler.error_handler_priv = "arm9tdmi_examine_debug_reason";
+ arm_jtag_set_instr(&arm7_9->jtag_info, arm7_9->jtag_info.intest_instr, &error_handler);
- jtag_add_dr_scan(3, fields, TAP_PD);
+ jtag_add_dr_scan(3, fields, TAP_PD, NULL);
jtag_execute_queue();
fields[0].in_value = NULL;
fields[2].in_value = NULL;
fields[2].out_value = instructionbus;
- jtag_add_dr_scan(3, fields, TAP_PD);
+ jtag_add_dr_scan(3, fields, TAP_PD, NULL);
if (debug_reason & 0x4)
if (debug_reason & 0x2)
/* put an instruction in the ARM9TDMI pipeline or write the data bus, and optionally read data */
int arm9tdmi_clock_out(arm_jtag_t *jtag_info, u32 instr, u32 out, u32 *in, int sysspeed)
{
+ error_handler_t error_handler;
scan_field_t fields[3];
u8 out_buf[4];
u8 instr_buf[4];
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+
+ error_handler.error_handler = arm9tdmi_jtag_error_handler;
+ error_handler.error_handler_priv = "arm9tdmi_clock_out";
+
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_runtest(0, -1);
int arm9tdmi_clock_data_in(arm_jtag_t *jtag_info, u32 *in)
{
scan_field_t fields[3];
+ error_handler_t error_handler;
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+
+ error_handler.error_handler = arm9tdmi_jtag_error_handler;
+ error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
+
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_runtest(0, -1);
int arm9tdmi_clock_data_in_endianness(arm_jtag_t *jtag_info, void *in, int size, int be)
{
scan_field_t fields[3];
-
+ error_handler_t error_handler;
+
jtag_add_end_state(TAP_PD);
arm_jtag_scann(jtag_info, 0x1);
- arm_jtag_set_instr(jtag_info, jtag_info->intest_instr);
+
+ error_handler.error_handler = arm9tdmi_jtag_error_handler;
+ error_handler.error_handler_priv = "arm9tdmi_clock_data_in_endianness";
+
+ arm_jtag_set_instr(jtag_info, jtag_info->intest_instr, &error_handler);
fields[0].device = jtag_info->chain_pos;
fields[0].num_bits = 32;
fields[2].in_handler = NULL;
fields[2].in_handler_priv = NULL;
- jtag_add_dr_scan(3, fields, -1);
+ jtag_add_dr_scan(3, fields, -1, NULL);
jtag_add_runtest(0, -1);
(*cache_p)->next = embeddedice_build_reg_cache(target, arm7_9);
arm7_9->eice_cache = (*cache_p)->next;
- if (arm7_9->has_etm)
- {
- (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, 0);
- arm7_9->etm_cache = (*cache_p)->next->next;
- }
-
- if (arm7_9->etb)
+ if (arm7_9->etm_ctx)
{
- (*cache_p)->next->next->next = etb_build_reg_cache(arm7_9->etb);
- arm7_9->etb->reg_cache = (*cache_p)->next->next->next;
+ (*cache_p)->next->next = etm_build_reg_cache(target, jtag_info, arm7_9->etm_ctx);
+ arm7_9->etm_ctx->reg_cache = (*cache_p)->next->next;
}
}
arm7_9->post_restore_context = NULL;
/* initialize arch-specific breakpoint handling */
- buf_set_u32((u8*)(&arm7_9->arm_bkpt), 0, 32, 0xdeeedeee);
- buf_set_u32((u8*)(&arm7_9->thumb_bkpt), 0, 16, 0xdeee);
+ arm7_9->arm_bkpt = 0xdeeedeee;
+ arm7_9->thumb_bkpt = 0xdeee;
arm7_9->sw_bkpts_use_wp = 1;
arm7_9->sw_bkpts_enabled = 0;