cross-build.sh: fix build with capstone

[openocd.git] / src / target / arm_adi_v5.c

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 0d458e2b5f8066f1c8bdedf8c4f375ddd371a96a..8d6d6618bca1c689c574dcec2d45d0ba7397ac37 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1107,14 +1107,6 @@ static int dap_read_part_id(struct adiv5_ap *ap, target_addr_t component_base, u
  * from chip observation (e.g. TI SDTI).
  */
 
-/* The legacy code only used the part number field to identify CoreSight peripherals.
- * This meant that the same part number from two different manufacturers looked the same.
- * It is desirable for all future additions to identify with both part number and JEP106.
- * "ANY_ID" is a wildcard (any JEP106) only to preserve legacy behavior for legacy entries.
- */
-
-#define ANY_ID 0x1000
-
 static const struct dap_part_nums {
        uint16_t designer_id;
        uint16_t part_num;
@@ -1131,9 +1123,12 @@ static const struct dap_part_nums {
        { ARM_ID, 0x00c, "Cortex-M4 SCS",              "(System Control Space)", },
        { ARM_ID, 0x00d, "CoreSight ETM11",            "(Embedded Trace)", },
        { ARM_ID, 0x00e, "Cortex-M7 FPB",              "(Flash Patch and Breakpoint)", },
+       { ARM_ID, 0x193, "SoC-600 TSGEN",              "(Timestamp Generator)", },
        { ARM_ID, 0x470, "Cortex-M1 ROM",              "(ROM Table)", },
        { ARM_ID, 0x471, "Cortex-M0 ROM",              "(ROM Table)", },
        { ARM_ID, 0x490, "Cortex-A15 GIC",             "(Generic Interrupt Controller)", },
+       { ARM_ID, 0x492, "Cortex-R52 GICD",            "(Distributor)", },
+       { ARM_ID, 0x493, "Cortex-R52 GICR",            "(Redistributor)", },
        { ARM_ID, 0x4a1, "Cortex-A53 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4a2, "Cortex-A57 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4a3, "Cortex-A53 ROM",             "(v7 Memory Map ROM Table)", },
@@ -1142,6 +1137,7 @@ static const struct dap_part_nums {
        { ARM_ID, 0x4aa, "Cortex-A35 ROM",             "(v8 Memory Map ROM Table)", },
        { ARM_ID, 0x4af, "Cortex-A15 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4b5, "Cortex-R5 ROM",              "(ROM Table)", },
+       { ARM_ID, 0x4b8, "Cortex-R52 ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c0, "Cortex-M0+ ROM",             "(ROM Table)", },
        { ARM_ID, 0x4c3, "Cortex-M3 ROM",              "(ROM Table)", },
        { ARM_ID, 0x4c4, "Cortex-M4 ROM",              "(ROM Table)", },
@@ -1187,11 +1183,25 @@ static const struct dap_part_nums {
        { ARM_ID, 0x9a9, "Cortex-M7 TPIU",             "(Trace Port Interface Unit)", },
        { ARM_ID, 0x9ae, "Cortex-A17 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9af, "Cortex-A15 PMU",             "(Performance Monitor Unit)", },
+       { ARM_ID, 0x9b6, "Cortex-R52 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
        { ARM_ID, 0x9b7, "Cortex-R7 PMU",              "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d3, "Cortex-A53 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d7, "Cortex-A57 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9d8, "Cortex-A72 PMU",             "(Performance Monitor Unit)", },
        { ARM_ID, 0x9da, "Cortex-A35 PMU/CTI/ETM",     "(Performance Monitor Unit/Cross Trigger/ETM)", },
+       { ARM_ID, 0x9e2, "SoC-600 APB-AP",             "(APB4 Memory Access Port)", },
+       { ARM_ID, 0x9e3, "SoC-600 AHB-AP",             "(AHB5 Memory Access Port)", },
+       { ARM_ID, 0x9e4, "SoC-600 AXI-AP",             "(AXI Memory Access Port)", },
+       { ARM_ID, 0x9e5, "SoC-600 APv1 Adapter",       "(Access Port v1 Adapter)", },
+       { ARM_ID, 0x9e6, "SoC-600 JTAG-AP",            "(JTAG Access Port)", },
+       { ARM_ID, 0x9e7, "SoC-600 TPIU",               "(Trace Port Interface Unit)", },
+       { ARM_ID, 0x9e8, "SoC-600 TMC ETR/ETS",        "(Embedded Trace Router/Streamer)", },
+       { ARM_ID, 0x9e9, "SoC-600 TMC ETB",            "(Embedded Trace Buffer)", },
+       { ARM_ID, 0x9ea, "SoC-600 TMC ETF",            "(Embedded Trace FIFO)", },
+       { ARM_ID, 0x9eb, "SoC-600 ATB Funnel",         "(Trace Funnel)", },
+       { ARM_ID, 0x9ec, "SoC-600 ATB Replicator",     "(Trace Replicator)", },
+       { ARM_ID, 0x9ed, "SoC-600 CTI",                "(Cross Trigger)", },
+       { ARM_ID, 0x9ee, "SoC-600 CATU",               "(Address Translation Unit)", },
        { ARM_ID, 0xc05, "Cortex-A5 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc07, "Cortex-A7 Debug",            "(Debug Unit)", },
        { ARM_ID, 0xc08, "Cortex-A8 Debug",            "(Debug Unit)", },
@@ -1206,6 +1216,11 @@ static const struct dap_part_nums {
        { ARM_ID, 0xd07, "Cortex-A57 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd08, "Cortex-A72 Debug",           "(Debug Unit)", },
        { ARM_ID, 0xd0b, "Cortex-A76 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd0c, "Neoverse N1",                "(Debug Unit)", },
+       { ARM_ID, 0xd13, "Cortex-R52 Debug",           "(Debug Unit)", },
+       { ARM_ID, 0xd49, "Neoverse N2",                "(Debug Unit)", },
+       { 0x017,  0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
+       { 0x017,  0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
        { 0x017,  0x9af, "MSP432 ROM",                 "(ROM Table)" },
        { 0x01f,  0xcd0, "Atmel CPU with DSU",         "(CPU)" },
        { 0x041,  0x1db, "XMC4500 ROM",                "(ROM Table)" },
@@ -1222,9 +1237,6 @@ static const struct dap_part_nums {
        { 0x1eb,  0x211, "Tegra 210 ROM",              "(ROM Table)", },
        { 0x1eb,  0x302, "Denver Debug",               "(Debug Unit)", },
        { 0x1eb,  0x402, "Denver PMU",                 "(Performance Monitor Unit)", },
-       /* legacy comment: 0x113: what? */
-       { ANY_ID, 0x120, "TI SDTI",                    "(System Debug Trace Interface)", }, /* from OMAP3 memmap */
-       { ANY_ID, 0x343, "TI DAPCTL",                  "", }, /* from OMAP3 memmap */
 };
 
 static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, unsigned int part_num)
@@ -1234,12 +1246,10 @@ static const struct dap_part_nums *pidr_to_part_num(unsigned int designer_id, un
                .full = "",
        };
 
-       for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++) {
-               if (dap_part_nums[i].designer_id != designer_id && dap_part_nums[i].designer_id != ANY_ID)
-                       continue;
-               if (dap_part_nums[i].part_num == part_num)
+       for (unsigned int i = 0; i < ARRAY_SIZE(dap_part_nums); i++)
+               if (dap_part_nums[i].designer_id == designer_id && dap_part_nums[i].part_num == part_num)
                        return &dap_part_nums[i];
-       }
+
        return &unknown;
 }