target/riscv: add common magic

[openocd.git] / src / target / arm_adi_v5.c

diff --git a/src/target/arm_adi_v5.c b/src/target/arm_adi_v5.c
index 01adbeff76b739e0dcedf105f8dde8a129bf4dce..cc5f0777504964f34ff8619b6e2b65f29a7ec422 100644 (file)
--- a/src/target/arm_adi_v5.c
+++ b/src/target/arm_adi_v5.c
@@ -1,3 +1,5 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
 /***************************************************************************
  *   Copyright (C) 2006 by Magnus Lundin                                   *
  *   lundin@mlu.mine.nu                                                    *
@@ -14,19 +16,6 @@
  *   andreas.fritiofson@gmail.com                                          *
  *                                                                         *
  *   Copyright (C) 2019-2021, Ampere Computing LLC                         *
- *                                                                         *
- *   This program is free software; you can redistribute it and/or modify  *
- *   it under the terms of the GNU General Public License as published by  *
- *   the Free Software Foundation; either version 2 of the License, or     *
- *   (at your option) any later version.                                   *
- *                                                                         *
- *   This program is distributed in the hope that it will be useful,       *
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of        *
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the         *
- *   GNU General Public License for more details.                          *
- *                                                                         *
- *   You should have received a copy of the GNU General Public License     *
- *   along with this program.  If not, see <http://www.gnu.org/licenses/>. *
  ***************************************************************************/
 
 /**
@@ -420,6 +409,26 @@ static int mem_ap_write(struct adiv5_ap *ap, const uint8_t *buffer, uint32_t siz
                                outvalue |= (uint32_t)*buffer++ << 8 * (0 ^ (drw_byte_idx & 3) ^ addr_xor);
                                break;
                        }
+               } else if (dap->nu_npcx_quirks) {
+                       switch (this_size) {
+                       case 4:
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
+                               break;
+                       case 2:
+                               outvalue |= (uint32_t)*buffer << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*(buffer+1) << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
+                               break;
+                       case 1:
+                               outvalue |= (uint32_t)*buffer << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer << 8 * (drw_byte_idx++ & 3);
+                               outvalue |= (uint32_t)*buffer++ << 8 * (drw_byte_idx & 3);
+                       }
                } else {
                        switch (this_size) {
                        case 4:
@@ -930,6 +939,7 @@ static const struct {
 #define DEVARCH_ID_MASK         (ARM_CS_C9_DEVARCH_ARCHITECT_MASK | ARM_CS_C9_DEVARCH_ARCHID_MASK)
 #define DEVARCH_MEM_AP          ARCH_ID(ARM_ID, 0x0A17)
 #define DEVARCH_ROM_C_0X9       ARCH_ID(ARM_ID, 0x0AF7)
+#define DEVARCH_UNKNOWN_V2      ARCH_ID(ARM_ID, 0x0A47)
 
 static const char *class0x9_devarch_description(uint32_t devarch)
 {
@@ -1844,8 +1854,16 @@ static int rtp_cs_component(enum coresight_access_mode mode, const struct rtp_op
                if ((v.devarch & ARM_CS_C9_DEVARCH_PRESENT) == 0)
                        return ERROR_OK;
 
-               if (is_mem_ap && (v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
-                       *is_mem_ap = true;
+               if (is_mem_ap) {
+                       if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_MEM_AP)
+                               *is_mem_ap = true;
+
+                       /* SoC-600 APv1 Adapter */
+                       if ((v.devarch & DEVARCH_ID_MASK) == DEVARCH_UNKNOWN_V2 &&
+                                       ARM_CS_PIDR_DESIGNER(v.pid) == ARM_ID &&
+                                       ARM_CS_PIDR_PART(v.pid) == 0x9e5)
+                               *is_mem_ap = true;
+               }
 
                /* quit if not ROM table */
                if ((v.devarch & DEVARCH_ID_MASK) != DEVARCH_ROM_C_0X9)
@@ -1880,7 +1898,7 @@ static int rtp_ap(const struct rtp_ops *ops, struct adiv5_ap *ap, int depth)
 
                if (!is_mem_ap)
                        return ERROR_OK;
-               /* Continue for an ADIv6 MEM-AP */
+               /* Continue for an ADIv6 MEM-AP or SoC-600 APv1 Adapter */
        }
 
        /* Now we read ROM table ID registers, ref. ARM IHI 0029B sec  */
@@ -2757,6 +2775,13 @@ COMMAND_HANDLER(dap_ti_be_32_quirks_command)
                "TI BE-32 quirks mode");
 }
 
+COMMAND_HANDLER(dap_nu_npcx_quirks_command)
+{
+       struct adiv5_dap *dap = adiv5_get_dap(CMD_DATA);
+       return CALL_COMMAND_HANDLER(handle_command_parse_bool, &dap->nu_npcx_quirks,
+                                                               "Nuvoton NPCX quirks mode");
+}
+
 const struct command_registration dap_instance_commands[] = {
        {
                .name = "info",
@@ -2829,5 +2854,12 @@ const struct command_registration dap_instance_commands[] = {
                .help = "set/get quirks mode for TI TMS450/TMS570 processors",
                .usage = "[enable]",
        },
+       {
+               .name = "nu_npcx_quirks",
+               .handler = dap_nu_npcx_quirks_command,
+               .mode = COMMAND_CONFIG,
+               .help = "set/get quirks mode for Nuvoton NPCX controllers",
+               .usage = "[enable]",
+       },
        COMMAND_REGISTRATION_DONE
 };